Messages in this thread | | | Date | Wed, 29 Mar 2023 14:13:14 +0800 | Subject | Re: [PATCH v2 4/8] iommu/vt-d: Reserve RID_PASID from global SVA PASID space | From | Baolu Lu <> |
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On 3/29/23 4:52 AM, Jacob Pan wrote: > On Tue, 28 Mar 2023 09:29:19 -0700, Jacob Pan > <jacob.jun.pan@linux.intel.com> wrote: > >>>> On VT-d platforms, RID_PASID is used for DMA request without PASID. We >>>> should not treat RID_PASID special instead let it be allocated from >>>> the global SVA PASID number space. >>> It's same to AMD and ARM SMMUv3, right? They also need an explicit >>> reservation of PASID 0. >>> >> yes, all IOMMU drivers need to do that. I will give it a try but might >> need help to place the call. > It might be simpler to just let SVA code allocate from 1 up instead of 0 > (as is in the current code). Global PASID allocator would still allow the > full range from 0 to max. Then there is no change to architectures that > don't support non-zero RID_PASID. For VT-d, it would still work in the > future when we have nonzero RID_PASID. is that reasonable?
Yes. It's reasonable from the status quo.
Best regards, baolu
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