Messages in this thread | | | Date | Tue, 28 Mar 2023 18:04:45 +0800 | Subject | Re: [PATCH v2] KVM: x86/pmu: Fix emulation on Intel counters' bit width | From | Like Xu <> |
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On 28/3/2023 5:20 pm, Paolo Bonzini wrote: > On 3/28/23 11:16, Like Xu wrote: >> >> >> If IA32_PERF_CAPABILITIES.FW_WRITE[bit 13] =1, each IA32_PMCi is accompanied by a >> corresponding alias address starting at 4C1H for IA32_A_PMC0. >> >> The bit width of the performance monitoring counters is specified in >> CPUID.0AH:EAX[23:16]. >> If IA32_A_PMCi is present, the 64-bit input value (EDX:EAX) of WRMSR to >> IA32_A_PMCi will cause >> IA32_PMCi to be updated by: >> >> COUNTERWIDTH = >> CPUID.0AH:EAX[23:16] bit width of the performance monitoring counter >> IA32_PMCi[COUNTERWIDTH-1:32] := EDX[COUNTERWIDTH-33:0]); >> IA32_PMCi[31:0] := EAX[31:0]; >> EDX[63:COUNTERWIDTH] are reserved >> >> --- >> >> Some might argue that this is all talking about GP counters, not >> fixed counters. In fact, the full-width write hw behaviour is >> presumed to do the same thing for all counters. > But the above behavior, and the #GP, is only true for IA32_A_PMCi (the > full-witdh MSR). Did I understand correctly that the behavior for fixed > counters is changed without introducing an alias MSR? > > Paolo >
If true, why introducing those alias MSRs ? My archaeological findings are:
a platform w/o full-witdh like Westmere (has 3-fixed counters already) is declared to have a counter width (R:48, W:32) and its successor Sandy Bridge has (R:48 , W: 32/48).
Thus I think the behaviour of the fixed counter has changed from there, and the alias GP MSRs were introduced to keep the support on 32-bit writes on #GP counters (via original address).
[*] Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes (252046-030, January 2011) Table 30-18 Core PMU Comparison.
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