Messages in this thread | | | Date | Fri, 24 Mar 2023 16:50:22 +0800 | Subject | Re: [PATCH 1/1] iommu/vt-d: Allow zero SAGAW if second-stage not supported | From | Baolu Lu <> |
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On 2023/3/24 12:49, Tian, Kevin wrote: >> From: Lu Baolu <baolu.lu@linux.intel.com> >> Sent: Saturday, March 18, 2023 10:48 AM >> >> The VT-d spec states (section 11.4.2) that hardware implementations >> reporting second-stage translation support (SSTS) field as Clear also >> report the SAGAW field as 0. Reflect this in the sanity check of >> alloc_iommu(). >> >> Fixes: 792fb43ce2c9 ("iommu/vt-d: Enable Intel IOMMU scalable mode by >> default") >> Suggested-by: Raghunathan Srinivasan <raghunathan.srinivasan@intel.com> >> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> >> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> >> --- >> drivers/iommu/intel/dmar.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c >> index 6acfe879589c..23828d189c2a 100644 >> --- a/drivers/iommu/intel/dmar.c >> +++ b/drivers/iommu/intel/dmar.c >> @@ -1071,7 +1071,8 @@ static int alloc_iommu(struct dmar_drhd_unit >> *drhd) >> } >> >> err = -EINVAL; >> - if (cap_sagaw(iommu->cap) == 0) { >> + if (!cap_sagaw(iommu->cap) && >> + (!ecap_smts(iommu->ecap) || ecap_slts(iommu->ecap))) { >> pr_info("%s: No supported address widths. Not attempting >> DMA translation.\n", >> iommu->name); >> drhd->ignored = 1; > > Reviewed-by: Kevin Tian <kevin.tian@intel.com> > > btw I wonder whether it's cleaner to record separate agaw values for > stage1/stage2 instead of picking a minimal set from both in > __iommu_calculate_sagaw().
That's better. The agaw could be picked according to which stage the domain is used for translation.
Best regards, baolu
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