Messages in this thread | | | Date | Wed, 22 Mar 2023 08:45:32 -0700 | From | Colin Foster <> | Subject | Re: [PATCH v1 mfd] mfd: ocelot-spi: fix bulk read |
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On Wed, Mar 22, 2023 at 05:25:51PM +0200, Vladimir Oltean wrote: > On Wed, Mar 22, 2023 at 07:11:30AM -0700, Colin Foster wrote: > > Ocelot chips (VSC7511, VSC7512, VSC7513, VSC7514) don't support bulk read > > operations over SPI. > > > > Many SPI buses have hardware that can optimize consecutive reads. > > Essentially an address is written to the chip, and if the SPI controller > > continues to toggle the clock, subsequent register values are reported. > > This can lead to significant optimizations, because the time between > > "address is written to the chip" and "chip starts to report data" can often > > take a fixed amount of time. > > > > When support for Ocelot chips were added in commit f3e893626abe ("mfd: > > ocelot: Add support for the vsc7512 chip via spi") it was believed that > > this optimization was supported. However it is not. > > Details? What about bulk reads is "not supported", and not supported by whom?
The chip itself doesn't support bulk reads. Every register read must be "Chip Select \" > "Read+Address Command" > "Padding" > "One Register Value" > "Chip Select /"
Figure 74 of [1] shows "SI Read Timing in Fast Mode", but that is when the VSC751X is the SPI controller, not a SPI endpoint. i.e. when the VSC751X is reading _from_ an external flash chip. It also has a blurb about "After reading address n, the SI boot controller automatically continues reading address n+1".
Figure 63 shows "Read Sequence for One-Byte Padding" which is actually done when an external CPU is reading _from_ the VSC751X devices. There is no suggestion that address n+1 will be returned in this scenario.
[1] https://ww1.microchip.com/downloads/en/DeviceDoc/VMDS-10489.pdf
I can update the commit message as needed.
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