Messages in this thread | | | From | Álvaro Fernández Rojas <> | Date | Wed, 22 Mar 2023 18:17:43 +0100 | Subject | Re: [PATCH v3 4/4] clk: bcm: Add BCM63268 timer clock and reset driver |
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El mié, 22 mar 2023 a las 0:23, Stephen Boyd (<sboyd@kernel.org>) escribió: > > Quoting Florian Fainelli (2023-03-21 16:09:54) > > On 3/21/23 16:06, Stephen Boyd wrote: > > > Quoting Florian Fainelli (2023-03-21 16:00:29) > > >> > > >> These SoCs are big-endian, require native endian register access and > > >> have no posted writes within their bus logic (UBUS) and require no > > >> barriers, hence the use of __raw_readl() and __raw_writel() is adequate. > > >> > > > > > > Use ioread32be() then? > > > > BCM63xx drivers tend to use __raw_{read,write}l for consistency and to > > make it clear that no barriers, no endian swapping is necessary, I would > > prefer to remain consistent with that convention. > > Ok. > > Is the clk device big-endian? Or the CPU is big-endian? SoC being > big-endian sounds like the devices in the SoC are big-endian. I hope we > never plop this device down with a CPU that's litle-endian.
The SoC is big-endian. I've only worked with MIPS big-endian devices from Broadcom, so I'm not really sure, but this seems to be very BCM63268-specific... Other BCM63xx devices I know have separate clock and reset controllers, but not this kind of timer, clock and reset controller...
-- Álvaro
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