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    SubjectRe: [PATCH v4 16/36] mips: Implement the new page table range API
    On Sun, Mar 19, 2023 at 08:16:36PM +0000, Matthew Wilcox wrote:
    > On Sun, Mar 19, 2023 at 07:45:36PM +0100, Thomas Bogendoerfer wrote:
    > > On Fri, Mar 17, 2023 at 04:29:20PM +0100, Thomas Bogendoerfer wrote:
    > > > hmm, not sure if that would help. R4k style TLB has two PTEs mapped
    > > > per TLB entry. So by advancing per page __update_tlb() is called more
    > > > often than needed.
    > >
    > > btw. how big is nr going to be ? There are MIPS SoCs out there, which
    > > just have 16 TLBs...
    >
    > Oof. The biggest we're going to see for now is one less than PTRS_PER_PMD
    > (that'd be a PMD-sized allocation that's mapped askew with 1 page in
    > one PMD and n-1 pages in the adjacent PMD). That'd be 511 on x86 and
    > I presume something similar on MIPS. More than 16, for sure.

    biggest TLB I could find is 256 entries, which can map 512 pages.

    > Now, this isn't a new problem with this patchset. With fault-around,
    > we already call set_pte_at() N times. And we don't say which ones are
    > speculative entries vs the one actually faulted in.

    ic

    > But let's see if we can fix it. What if we passed in the vmf? That would
    > give you the actual faulting address, so you'd know to only put the PTE
    > into the Linux page tables and not go as far as putting it into the TLB.
    > Open to other ideas.

    that would help to optimize the case. But update_mmu_cache_range needs to
    do __update_tlb() for every page to avoid stale data in TLB. If I understood
    correctly only the way how TLB updates are done changed, so there shouldn't
    be performance regressions. And optimizing like moving the looping over
    the pages into __update_tlb() could be done in a second step.

    Thomas.

    --
    Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
    good idea. [ RFC1925, 2.3 ]

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