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    Subject[PATCH 05/10] mips: ralink: rt3883: remove clock related code
    Date
    A properly clock driver for ralink SoCs has been added. Hence there is no
    need to have clock related code in 'arch/mips/ralink' folder anymore.

    Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
    ---
    arch/mips/include/asm/mach-ralink/rt3883.h | 8 ----
    arch/mips/ralink/rt3883.c | 44 ----------------------
    2 files changed, 52 deletions(-)

    diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
    index ad25d5e8d2dc..4a835b178925 100644
    --- a/arch/mips/include/asm/mach-ralink/rt3883.h
    +++ b/arch/mips/include/asm/mach-ralink/rt3883.h
    @@ -92,14 +92,6 @@
    #define RT3883_REVID_VER_ID_SHIFT 8
    #define RT3883_REVID_ECO_ID_MASK 0x0f

    -#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
    -#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
    -#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
    -#define RT3883_SYSCFG0_CPUCLK_250 0x0
    -#define RT3883_SYSCFG0_CPUCLK_384 0x1
    -#define RT3883_SYSCFG0_CPUCLK_480 0x2
    -#define RT3883_SYSCFG0_CPUCLK_500 0x3
    -
    #define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
    #define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
    #define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
    diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c
    index cca887af378f..14c56993611a 100644
    --- a/arch/mips/ralink/rt3883.c
    +++ b/arch/mips/ralink/rt3883.c
    @@ -21,50 +21,6 @@

    static struct ralink_soc_info *soc_info_ptr;

    -void __init ralink_clk_init(void)
    -{
    - unsigned long cpu_rate, sys_rate;
    - u32 syscfg0;
    - u32 clksel;
    - u32 ddr2;
    -
    - syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
    - clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
    - RT3883_SYSCFG0_CPUCLK_MASK);
    - ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
    -
    - switch (clksel) {
    - case RT3883_SYSCFG0_CPUCLK_250:
    - cpu_rate = 250000000;
    - sys_rate = (ddr2) ? 125000000 : 83000000;
    - break;
    - case RT3883_SYSCFG0_CPUCLK_384:
    - cpu_rate = 384000000;
    - sys_rate = (ddr2) ? 128000000 : 96000000;
    - break;
    - case RT3883_SYSCFG0_CPUCLK_480:
    - cpu_rate = 480000000;
    - sys_rate = (ddr2) ? 160000000 : 120000000;
    - break;
    - case RT3883_SYSCFG0_CPUCLK_500:
    - cpu_rate = 500000000;
    - sys_rate = (ddr2) ? 166000000 : 125000000;
    - break;
    - }
    -
    - ralink_clk_add("cpu", cpu_rate);
    - ralink_clk_add("10000100.timer", sys_rate);
    - ralink_clk_add("10000120.watchdog", sys_rate);
    - ralink_clk_add("10000500.uart", 40000000);
    - ralink_clk_add("10000900.i2c", 40000000);
    - ralink_clk_add("10000a00.i2s", 40000000);
    - ralink_clk_add("10000b00.spi", sys_rate);
    - ralink_clk_add("10000b40.spi", sys_rate);
    - ralink_clk_add("10000c00.uartlite", 40000000);
    - ralink_clk_add("10100000.ethernet", sys_rate);
    - ralink_clk_add("10180000.wmac", 40000000);
    -}
    -
    void __init ralink_of_remap(void)
    {
    rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
    --
    2.25.1
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