Messages in this thread | | | Date | Thu, 16 Mar 2023 17:11:15 +0100 | Subject | Re: [PATCH] net: macb: Set MDIO clock divisor for pclk higher than 160MHz | From | Nicolas Ferre <> |
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On 16/03/2023 at 11:03, Bartosz Wawrzyniak wrote: > Currently macb sets clock divisor for pclk up to 160 MHz. > Function gem_mdc_clk_div was updated to enable divisor > for higher values of pclk. > > Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Looks good to me: Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Thanks for your patch. Best regards, Nicolas
> --- > drivers/net/ethernet/cadence/macb.h | 2 ++ > drivers/net/ethernet/cadence/macb_main.c | 6 +++++- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h > index 14dfec4db8f9..c1fc91c97cee 100644 > --- a/drivers/net/ethernet/cadence/macb.h > +++ b/drivers/net/ethernet/cadence/macb.h > @@ -692,6 +692,8 @@ > #define GEM_CLK_DIV48 3 > #define GEM_CLK_DIV64 4 > #define GEM_CLK_DIV96 5 > +#define GEM_CLK_DIV128 6 > +#define GEM_CLK_DIV224 7 > > /* Constants for MAN register */ > #define MACB_MAN_C22_SOF 1 > diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c > index 6e141a8bbf43..8708af6d25ed 100644 > --- a/drivers/net/ethernet/cadence/macb_main.c > +++ b/drivers/net/ethernet/cadence/macb_main.c > @@ -2641,8 +2641,12 @@ static u32 gem_mdc_clk_div(struct macb *bp) > config = GEM_BF(CLK, GEM_CLK_DIV48); > else if (pclk_hz <= 160000000) > config = GEM_BF(CLK, GEM_CLK_DIV64); > - else > + else if (pclk_hz <= 240000000) > config = GEM_BF(CLK, GEM_CLK_DIV96); > + else if (pclk_hz <= 320000000) > + config = GEM_BF(CLK, GEM_CLK_DIV128); > + else > + config = GEM_BF(CLK, GEM_CLK_DIV224); > > return config; > } > -- > 2.33.0 >
-- Nicolas Ferre
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