Messages in this thread Patch in this message | | | From | Konrad Dybcio <> | Date | Thu, 16 Mar 2023 15:12:58 +0100 | Subject | [PATCH v2 09/14] arm64: dts: qcom: sm6375: Add CPUCP L3 node |
| |
Configure the L3 cache DVFS scaler within the CPUCP block to allow for dynamic frequency switching.
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 90f18754a63b..59d7ed25aa36 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1505,6 +1505,15 @@ frame@f42d000 { }; }; + cpucp_l3: interconnect@fd90000 { + compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3"; + reg = <0 0x0fd90000 0 0x1000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@fd91000 { compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; -- 2.39.2
| |