Messages in this thread | | | Date | Wed, 15 Mar 2023 09:42:59 -0500 | Subject | Re: [PATCH v2] arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G | From | Andrew Davis <> |
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On 3/14/23 11:25 PM, Siddharth Vadapalli wrote: > Add device tree support to enable MCU CPSW with J784S4 EVM. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > Hello, > > Please do not merge this patch until the following have been merged: > 1. https://lore.kernel.org/r/20230314085500.10597-1-j-choudhary@ti.com/ > 2. https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/ > 3. https://lore.kernel.org/r/20230308201513.116638-1-j-choudhary@ti.com/ > > Changes from v1: > 1. Drop patch for adding device id property for mcu_navss. This patch is > now a part of another series at: > https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/ > 2. Move "mcu_mdio_pins_default" pinctrl to the "davinci_mdio" node. >
LGTM,
Reviewed-by: Andrew Davis <afd@ti.com>
> v1: > https://lore.kernel.org/r/20230314104055.1475054-1-s-vadapalli@ti.com/ > > arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 50 ++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts > index 8cd4a7ecc121..476ad8915c5b 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts > @@ -140,6 +140,32 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ > }; > }; > > +&wkup_pmx0 { > + mcu_cpsw_pins_default: mcu-cpsw-pins-default { > + pinctrl-single,pins = < > + J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ > + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ > + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ > + J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ > + J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ > + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ > + J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ > + J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ > + J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ > + J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ > + J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ > + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ > + >; > + }; > + > + mcu_mdio_pins_default: mcu-mdio-pins-default { > + pinctrl-single,pins = < > + J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ > + J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ > + >; > + }; > +}; > + > &main_uart8 { > status = "okay"; > pinctrl-names = "default"; > @@ -194,3 +220,27 @@ &main_sdhci1 { > &main_gpio0 { > status = "okay"; > }; > + > +&mcu_cpsw { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&mcu_cpsw_pins_default>; > +}; > + > +&davinci_mdio { > + pinctrl-names = "default"; > + pinctrl-0 = <&mcu_mdio_pins_default>; > + > + mcu_phy0: ethernet-phy@0 { > + reg = <0>; > + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; > + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > + ti,min-output-impedance; > + }; > +}; > + > +&mcu_cpsw_port1 { > + status = "okay"; > + phy-mode = "rgmii-rxid"; > + phy-handle = <&mcu_phy0>; > +};
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