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    Subject[PATCH v2 5/6] clk: starfive: jh7110-sys: Modify PLL clocks source
    Date
    Modify PLL clocks source to be got from dts instead of
    the fixed factor clocks.

    Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
    ---
    drivers/clk/starfive/Kconfig | 1 +
    .../clk/starfive/clk-starfive-jh7110-sys.c | 35 ++++---------------
    2 files changed, 7 insertions(+), 29 deletions(-)

    diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
    index e306edf4defa..903a5097c642 100644
    --- a/drivers/clk/starfive/Kconfig
    +++ b/drivers/clk/starfive/Kconfig
    @@ -35,6 +35,7 @@ config CLK_STARFIVE_JH7110_SYS
    select AUXILIARY_BUS
    select CLK_STARFIVE_JH71X0
    select RESET_STARFIVE_JH7110
    + select CLK_STARFIVE_JH7110_PLL
    default ARCH_STARFIVE
    help
    Say yes here to support the system clock controller on the
    diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
    index b90d8035ba18..4bd8ff5ff912 100644
    --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
    +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
    @@ -329,9 +329,6 @@ static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *d
    if (idx < JH7110_SYSCLK_END)
    return &priv->reg[idx].hw;

    - if (idx >= JH7110_SYSCLK_PLL0_OUT && idx <= JH7110_SYSCLK_PLL2_OUT)
    - return priv->pll[idx - JH7110_SYSCLK_PLL0_OUT];
    -
    return ERR_PTR(-EINVAL);
    }

    @@ -355,29 +352,6 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)

    dev_set_drvdata(priv->dev, (void *)(&priv->base));

    - /*
    - * These PLL clocks are not actually fixed factor clocks and can be
    - * controlled by the syscon registers of JH7110. They will be dropped
    - * and registered in the PLL clock driver instead.
    - */
    - /* 24MHz -> 1000.0MHz */
    - priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
    - "osc", 0, 125, 3);
    - if (IS_ERR(priv->pll[0]))
    - return PTR_ERR(priv->pll[0]);
    -
    - /* 24MHz -> 1066.0MHz */
    - priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
    - "osc", 0, 533, 12);
    - if (IS_ERR(priv->pll[1]))
    - return PTR_ERR(priv->pll[1]);
    -
    - /* 24MHz -> 1188.0MHz */
    - priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
    - "osc", 0, 99, 2);
    - if (IS_ERR(priv->pll[2]))
    - return PTR_ERR(priv->pll[2]);
    -
    for (idx = 0; idx < JH7110_SYSCLK_END; idx++) {
    u32 max = jh7110_sysclk_data[idx].max;
    struct clk_parent_data parents[4] = {};
    @@ -415,9 +389,12 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
    parents[i].fw_name = "tdm_ext";
    else if (pidx == JH7110_SYSCLK_MCLK_EXT)
    parents[i].fw_name = "mclk_ext";
    - else if (pidx >= JH7110_SYSCLK_PLL0_OUT &&
    - pidx <= JH7110_SYSCLK_PLL2_OUT)
    - parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
    + else if (pidx == JH7110_SYSCLK_PLL0_OUT)
    + parents[i].fw_name = "pll0_out";
    + else if (pidx == JH7110_SYSCLK_PLL1_OUT)
    + parents[i].fw_name = "pll1_out";
    + else if (pidx == JH7110_SYSCLK_PLL2_OUT)
    + parents[i].fw_name = "pll2_out";
    }

    clk->hw.init = &init;
    --
    2.25.1
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