Messages in this thread | | | From | Huacai Chen <> | Date | Wed, 15 Mar 2023 14:24:32 +0800 | Subject | Re: [PATCH V2] LoongArch: Make WriteCombine configurable for ioremap() |
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On Wed, Mar 15, 2023 at 12:33 PM Xi Ruoyao <xry111@xry111.site> wrote: > > On Wed, 2023-03-15 at 08:44 +0800, Huacai Chen wrote: > > /* snip */ > > > +config ARCH_WRITECOMBINE > > + bool "Enable WriteCombine (WUC) for ioremap()" > > + help > > + LoongArch maintains cache coherency in hardware, but when paired > > + with LS7A chipsets the WUC attribute (Weak-ordered UnCached, which > > + is similar to WriteCombine) is out of the scope of cache coherency > > + machanism for PCIe devices (this is a PCIe protocol violation, which > > + may be fixed in newer chipsets). > > + > > + This means WUC can only used for write-only memory regions now, so > > + this option is disabled by default, making WUC silently fallback to > > + SUC for ioremap(). You can enable this option if the kernel is ensured > > + to run on hardware without this bug. > > 'You can override this setting via writecombine=yes/no boot parameter.' OK, thanks.
> > /* snip */ > > > +static int __init setup_writecombine(char *p) > > +{ > > + if (!strcmp(p, "on")) > > + pgprot_wc = PAGE_KERNEL_WUC; > > + else if (!strcmp(p, "off")) > > + pgprot_wc = PAGE_KERNEL_SUC; > > else > pr_warn("Unknown writecombine setting \"%s\".\n", p); OK, thanks.
Huacai > > Otherwise LGTM. > > -- > Xi Ruoyao <xry111@xry111.site> > School of Aerospace Science and Technology, Xidian University
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