Messages in this thread Patch in this message | | | From | William Qiu <> | Subject | [RESEND v6 2/2] riscv: dts: starfive: Add syscon node | Date | Wed, 15 Mar 2023 13:58:13 +0800 |
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Add stg_syscon/sys_syscon/aon_syscon node for JH7110 Soc.
Signed-off-by: William Qiu <william.qiu@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index d484ecdf93f7..49dd62276b0d 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -362,6 +362,11 @@ i2c2: i2c@10050000 { status = "disabled"; };
+ stg_syscon: syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x0 0x10240000 0x0 0x1000>; + }; + uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>; @@ -466,6 +471,11 @@ syscrg: clock-controller@13020000 { #reset-cells = <1>; };
+ sys_syscon: syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon"; + reg = <0x0 0x13030000 0x0 0x1000>; + }; + sysgpio: pinctrl@13040000 { compatible = "starfive,jh7110-sys-pinctrl"; reg = <0x0 0x13040000 0x0 0x10000>; @@ -495,6 +505,11 @@ aoncrg: clock-controller@17000000 { #reset-cells = <1>; };
+ aon_syscon: syscon@17010000 { + compatible = "starfive,jh7110-aon-syscon", "syscon"; + reg = <0x0 0x17010000 0x0 0x1000>; + }; + aongpio: pinctrl@17020000 { compatible = "starfive,jh7110-aon-pinctrl"; reg = <0x0 0x17020000 0x0 0x10000>; -- 2.34.1
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