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    Subject[PATCH v8 09/14] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks
    Date
    The LLCC block has several banks each with a different base address
    and holes in between. So it is not a correct approach to cover these
    banks with a single offset/size. Instead, the individual bank's base
    address needs to be specified in devicetree with the exact size.

    Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
    Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
    ---
    arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +++++--
    1 file changed, 5 insertions(+), 2 deletions(-)

    diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
    index 1c97e28da6ad..3fefd8cbba6d 100644
    --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
    +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
    @@ -2204,8 +2204,11 @@ gem_noc: interconnect@9100000 {

    system-cache-controller@9200000 {
    compatible = "qcom,sm8350-llcc";
    - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
    - reg-names = "llcc_base", "llcc_broadcast_base";
    + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
    + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
    + <0 0x09600000 0 0x58000>;
    + reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
    + "llcc3_base", "llcc_broadcast_base";
    };

    compute_noc: interconnect@a0c0000 {
    --
    2.25.1
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