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    SubjectRe: [PATCH 2/6] tools/perf/json: Add cache metrics for s390 z16
    On Mon, Mar 13, 2023 at 1:30 AM Thomas Richter <tmricht@linux.ibm.com> wrote:
    >
    > Add metrics for s390 z16
    > - Percentage sourced from Level 2 cache
    > - Percentage sourced from Level 3 on same chip cache
    > - Percentage sourced from Level 4 Local cache on same book
    > - Percentage sourced from Level 4 Remote cache on different book
    > - Percentage sourced from memory
    >
    > For details about the formulas see this documentation:
    > https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf
    >
    > Outpuf after:
    > # ./perf stat -M l4rp -- dd if=/dev/zero of=/dev/null bs=10M count=10K
    > .... dd output deleted
    >
    > Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=10M count=10K':
    >
    > 0 IDCW_OFF_DRAWER_CHIP_HIT # 0.00 l4rp
    > 431,866 L1I_DIR_WRITES
    > 2,395 IDCW_OFF_DRAWER_IV
    > 0 ICW_OFF_DRAWER
    > 0 IDCW_OFF_DRAWER_DRAWER_HIT
    > 1,437 DCW_OFF_DRAWER
    > 425,960,793 L1D_DIR_WRITES
    >
    > 12.165030699 seconds time elapsed
    >
    > 0.001037000 seconds user
    > 12.162140000 seconds sys
    >
    > #
    >
    > Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
    > Acked-By: Sumanth Korikkar <sumanthk@linux.ibm.com>

    Acked-by: Ian Rogers <irogers@google.com>

    Thanks,
    Ian

    > ---
    > .../arch/s390/cf_z16/transaction.json | 25 +++++++++++++++++++
    > 1 file changed, 25 insertions(+)
    >
    > diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json
    > index 86bf83b4504e..dde0735a7d22 100644
    > --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json
    > +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json
    > @@ -18,5 +18,30 @@
    > "BriefDescription": "Level One Miss per 100 Instructions",
    > "MetricName": "l1mp",
    > "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100"
    > + },
    > + {
    > + "BriefDescription": "Percentage sourced from Level 2 cache",
    > + "MetricName": "l2p",
    > + "MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
    > + },
    > + {
    > + "BriefDescription": "Percentage sourced from Level 3 on same chip cache",
    > + "MetricName": "l3p",
    > + "MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
    > + },
    > + {
    > + "BriefDescription": "Percentage sourced from Level 4 Local cache on same book",
    > + "MetricName": "l4lp",
    > + "MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
    > + },
    > + {
    > + "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",
    > + "MetricName": "l4rp",
    > + "MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
    > + },
    > + {
    > + "BriefDescription": "Percentage sourced from memory",
    > + "MetricName": "memp",
    > + "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
    > }
    > ]
    > --
    > 2.39.1
    >

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