Messages in this thread Patch in this message | | | From | "Garg, Nemesa" <> | Subject | [PATCH dii-client 1/3] drm/pciid : Adding ARL-S and ARL-P PCI/device ids | Date | Wed, 1 Mar 2023 16:54:43 +0530 |
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Arrow Lake behaves the same as Meteor Lake with just minor differences. Add definitions for ARL_P. Update MTL and ARL definitions with new device IDs for ARL-S and ARL-P.
Bspec: 55420
Signed-off-by: Garg, Nemesa <nemesa.garg@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_device_info.c | 7 +++++++ drivers/gpu/drm/i915/intel_device_info.h | 1 + include/drm/i915_pciids.h | 11 +++++++++-- 4 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index da3ee9b27747..0490fa282663 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -574,6 +574,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M) #define IS_METEORLAKE_P(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P) +#define IS_ARROWLAKE_P(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_P) #define IS_DG2_G10(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10) #define IS_DG2_G11(dev_priv) \ diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 98769e5f2c3d..bda73201417f 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -224,6 +224,10 @@ static const u16 subplatform_p_ids[] = { INTEL_MTL_P_IDS(0), }; +static const u16 subplatform_arl_p_ids[] = { + INTEL_ARL_P_IDS(0), +}; + static bool find_devid(u16 id, const u16 *p, unsigned int num) { for (; num; num--, p++) { @@ -284,6 +288,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915) } else if (find_devid(devid, subplatform_p_ids, ARRAY_SIZE(subplatform_p_ids))) { mask = BIT(INTEL_SUBPLATFORM_P); + } else if (find_devid(devid, subplatform_arl_p_ids, + ARRAY_SIZE(subplatform_arl_p_ids))) { + mask = BIT(INTEL_SUBPLATFORM_ARL_P); } GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 80bda653d61b..eba718d98482 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -131,6 +131,7 @@ enum intel_platform { /* MTL */ #define INTEL_SUBPLATFORM_M 0 #define INTEL_SUBPLATFORM_P 1 +#define INTEL_SUBPLATFORM_ARL_P 2 enum intel_ppgtt_type { INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 92205054e542..cc3f01c7e98b 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -738,15 +738,22 @@ /* MTL */ #define INTEL_MTL_M_IDS(info) \ INTEL_VGA_DEVICE(0x7D40, info), \ - INTEL_VGA_DEVICE(0x7D60, info) + INTEL_VGA_DEVICE(0x7D41, info), \ + INTEL_VGA_DEVICE(0x7D60, info), \ + INTEL_VGA_DEVICE(0x7D67, info) #define INTEL_MTL_P_IDS(info) \ INTEL_VGA_DEVICE(0x7D45, info), \ INTEL_VGA_DEVICE(0x7D55, info), \ INTEL_VGA_DEVICE(0x7DD5, info) +#define INTEL_ARL_P_IDS(info) \ + INTEL_VGA_DEVICE(0x7D51, info), \ + INTEL_VGA_DEVICE(0x7DD1, info) + #define INTEL_MTL_IDS(info) \ INTEL_MTL_M_IDS(info), \ - INTEL_MTL_P_IDS(info) + INTEL_MTL_P_IDS(info), \ + INTEL_ARL_P_IDS(info) #endif /* _I915_PCIIDS_H */
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