Messages in this thread | | | Date | Thu, 14 Dec 2023 19:18:19 +0100 | Subject | Re: [PATCH v3 7/8] arm64: dts: qcom: ipq5332: add support for the NSSCC | From | Konrad Dybcio <> |
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On 12/11/23 14:28, Kathiravan Thirumoorthy wrote: > > > On 12/11/2023 4:02 PM, Konrad Dybcio wrote: >> On 11.12.2023 04:37, Kathiravan Thirumoorthy wrote: >>> Describe the NSS clock controller node and it's relevant external >>> clocks. >>> >>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++ >>> 1 file changed, 28 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi >>> index 42e2e48b2bc3..a1504f6c40c1 100644 >>> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi >>> @@ -15,6 +15,18 @@ / { >>> #size-cells = <2>; >>> clocks { >>> + cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk { >>> + compatible = "fixed-clock"; >>> + clock-frequency = <200000000>; >>> + #clock-cells = <0>; >>> + }; >>> + >>> + cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk { >>> + compatible = "fixed-clock"; >>> + clock-frequency = <300000000>; >>> + #clock-cells = <0>; >>> + }; >>> + >>> sleep_clk: sleep-clk { >>> compatible = "fixed-clock"; >>> #clock-cells = <0>; >>> @@ -473,6 +485,22 @@ frame@b128000 { >>> status = "disabled"; >>> }; >>> }; >>> + >>> + nsscc: clock-controller@39b00000{ >> Missing space between the opening curly brace > > My bad :( will fix it in next spin. > >> >>> + compatible = "qcom,ipq5332-nsscc"; >>> + reg = <0x39b00000 0x80000>; >> the regmap_config in the clk driver has .max_register = 0x800, is this >> correct? > > As per the memory map, 512KB is the size of this block. However the last register in that region is at the offset 0x800. Shall I update the max_register also to 512KB to keep it consistency? No, it's fine, I just wanted to know if it's intentional :)
Thanks!
Konrad
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