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    Subject[PATCH v6 10/38] arm64/cpufeature: Runtime detection of Guarded Control Stack (GCS)
    Add a cpufeature for GCS, allowing other code to conditionally support it
    at runtime.

    Signed-off-by: Mark Brown <broonie@kernel.org>
    ---
    arch/arm64/include/asm/cpufeature.h | 6 ++++++
    arch/arm64/kernel/cpufeature.c | 16 ++++++++++++++++
    arch/arm64/tools/cpucaps | 1 +
    3 files changed, 23 insertions(+)

    diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
    index 5bba39376055..4a5eea41f8ed 100644
    --- a/arch/arm64/include/asm/cpufeature.h
    +++ b/arch/arm64/include/asm/cpufeature.h
    @@ -831,6 +831,12 @@ static inline bool system_supports_tlb_range(void)
    cpus_have_const_cap(ARM64_HAS_TLB_RANGE);
    }

    +static inline bool system_supports_gcs(void)
    +{
    + return IS_ENABLED(CONFIG_ARM64_GCS) &&
    + cpus_have_const_cap(ARM64_HAS_GCS);
    +}
    +
    int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
    bool try_emulate_mrs(struct pt_regs *regs, u32 isn);

    diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
    index 444a73c2e638..e247dce1759c 100644
    --- a/arch/arm64/kernel/cpufeature.c
    +++ b/arch/arm64/kernel/cpufeature.c
    @@ -255,6 +255,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
    };

    static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
    + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS),
    + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0),
    ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0),
    ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0),
    @@ -2220,6 +2222,12 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused)
    sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);
    }

    +static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused)
    +{
    + /* GCS is not currently used at EL1 */
    + write_sysreg_s(0, SYS_GCSCR_EL1);
    +}
    +
    /* Internal helper functions to match cpu capability type */
    static bool
    cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
    @@ -2719,6 +2727,14 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
    .matches = has_cpuid_feature,
    ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP)
    },
    + {
    + .desc = "Guarded Control Stack (GCS)",
    + .capability = ARM64_HAS_GCS,
    + .type = ARM64_CPUCAP_SYSTEM_FEATURE,
    + .cpu_enable = cpu_enable_gcs,
    + .matches = has_cpuid_feature,
    + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP)
    + },
    {},
    };

    diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
    index c3f06fdef609..9b470b311f29 100644
    --- a/arch/arm64/tools/cpucaps
    +++ b/arch/arm64/tools/cpucaps
    @@ -27,6 +27,7 @@ HAS_ECV_CNTPOFF
    HAS_EPAN
    HAS_EVT
    HAS_FGT
    +HAS_GCS
    HAS_GENERIC_AUTH
    HAS_GENERIC_AUTH_ARCH_QARMA3
    HAS_GENERIC_AUTH_ARCH_QARMA5
    --
    2.30.2

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