Messages in this thread | | | Date | Tue, 31 Oct 2023 18:17:01 +0100 | Subject | Re: [RFC PATCH 5/5] arm64: dts: qcom: ipq9574: Add support for SPI nand | From | Krzysztof Kozlowski <> |
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On 31/10/2023 13:03, Md Sadre Alam wrote: > Add support for QPIC SPI NAND for IPQ9574 > > Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> > Signed-off-by: Sricharan R <quic_srichara@quicinc.com> > --- > arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 56 ++++++++++----------- > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 30 ++++++++++- > 2 files changed, 57 insertions(+), 29 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > index 1bb8d96c9a82..5e4200edb873 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > @@ -15,48 +15,48 @@ / { > compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; > }; > > -&sdhc_1 { > - pinctrl-0 = <&sdc_default_state>; > - pinctrl-names = "default"; > - mmc-ddr-1_8v; > - mmc-hs200-1_8v; > - mmc-hs400-1_8v; > - mmc-hs400-enhanced-strobe; > - max-frequency = <384000000>; > - bus-width = <8>; > - status = "okay";
Why? This is not explained in commit msg.
> -}; > - > &tlmm { > - sdc_default_state: sdc-default-state { > - clk-pins { > + qspi_nand_pins: qspi_nand_pins { > + spi_clock { > pins = "gpio5"; > - function = "sdc_clk"; > + function = "qspi_clk";
Why?
> drive-strength = <8>; > bias-disable; > }; > > - cmd-pins { > + qspi_cs {
No, come one. Code was good and you replace it to incorrect one. Please stop bringing more issues to fix.
> pins = "gpio4"; > - function = "sdc_cmd"; > + function = "qspi_cs"; > drive-strength = <8>; > bias-pull-up; > }; >
...
> + > bch: qpic_ecc { > compatible = "qcom,ipq9574-ecc"; > status = "ok"; > - } > + };
This is the saddest part of the entire patchset...
> > blsp_dma: dma-controller@7884000 { > compatible = "qcom,bam-v1.7.0";
Best regards, Krzysztof
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