Messages in this thread | | | Date | Tue, 3 Oct 2023 22:59:47 +0530 | Subject | Re: [PATCH 5/6] arm64: dts: qcom: ipq5018: Add PCIe related nodes | From | Nitheesh Sekar <> |
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On 10/3/2023 8:53 PM, Dmitry Baryshkov wrote: > On Tue, 3 Oct 2023 at 15:10, Nitheesh Sekar <quic_nsekar@quicinc.com> wrote: >> Add phy and controller nodes for PCIe_x2 and PCIe_x1. >> PCIe_x2 is 2-lane Gen2 and PCIe_x1 is 1-lane Gen2. >> >> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 186 +++++++++++++++++++++++++- >> 1 file changed, 184 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> index 38ffdc3cbdcd..0818fdd1e693 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> @@ -8,6 +8,7 @@ >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/clock/qcom,gcc-ipq5018.h> >> #include <dt-bindings/reset/qcom,gcc-ipq5018.h> >> +#include <dt-bindings/gpio/gpio.h> >> >> / { >> interrupt-parent = <&intc>; >> @@ -94,6 +95,38 @@ >> #size-cells = <1>; >> ranges = <0 0 0 0xffffffff>; >> >> + pcie_x1phy: phy@7e000{ >> + compatible = "qcom,ipq5018-uniphy-pcie-gen2x1"; >> + reg = <0x0007e000 0x800>; >> + #phy-cells = <0>; >> + #clock-cells = <0>; >> + clocks = <&gcc GCC_PCIE1_PIPE_CLK>; >> + clock-names = "pipe_clk"; >> + clock-output-names = "pcie1_pipe_clk"; >> + assigned-clocks = <&gcc GCC_PCIE1_PIPE_CLK>; >> + assigned-clock-rates = <125000000>; >> + resets = <&gcc GCC_PCIE1_PHY_BCR>, >> + <&gcc GCC_PCIE1PHY_PHY_BCR>; >> + reset-names = "phy", "phy_phy"; >> + status = "disabled"; >> + }; >> + >> + pcie_x2phy: phy@86000{ >> + compatible = "qcom,ipq5018-uniphy-pcie-gen2x2"; >> + reg = <0x00086000 0x800>; >> + #phy-cells = <0>; >> + #clock-cells = <0>; >> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; >> + clock-names = "pipe_clk"; >> + clock-output-names = "pcie0_pipe_clk"; >> + assigned-clocks = <&gcc GCC_PCIE0_PIPE_CLK>; >> + assigned-clock-rates = <125000000>; > Can this go into the PHY driver? Sure. Will check and update. > >> + resets = <&gcc GCC_PCIE0_PHY_BCR>, >> + <&gcc GCC_PCIE0PHY_PHY_BCR>; >> + reset-names = "phy", "phy_phy"; >> + status = "disabled"; >> + }; >> + >> tlmm: pinctrl@1000000 { >> compatible = "qcom,ipq5018-tlmm"; >> reg = <0x01000000 0x300000>; >> @@ -117,8 +150,8 @@ >> reg = <0x01800000 0x80000>; >> clocks = <&xo_board_clk>, >> <&sleep_clk>, >> - <0>, >> - <0>, >> + <&pcie_x2phy>, >> + <&pcie_x1phy>, >> <0>, >> <0>, >> <0>, >> @@ -246,6 +279,155 @@ >> status = "disabled"; >> }; >> }; >> + >> + pcie_x1: pci@80000000 { >> + compatible = "qcom,pcie-ipq5018"; >> + reg = <0x80000000 0xf1d > Each address/size tuple should be a separate <> entry. Sure. will update it. > >> + 0x80000F20 0xa8 > lowercase Sure. Will update. > >> + 0x80001000 0x1000 >> + 0x78000 0x3000 > Would you notice why this line stands away from the rest of entries here?
Sure. Will pad it Zeros.
Thanks, Nitheesh
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