Messages in this thread | | | From | Thomas Gleixner <> | Subject | Re: [PATCH v2] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs. | Date | Fri, 27 Oct 2023 10:16:57 +0200 |
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On Fri, Oct 27 2023 at 11:10, Fang Xiang wrote: > In non-coherent GIC design, ITS tables should be clean and flushed > to the PoV of the ITS before writing GITS_BASER<n> registers. And > hoist the quirked non-shareable attributes earlier to save effort > in tables setup. > > Signed-off-by: Fang Xiang <fangxiang3@xiaomi.com>
Seriously? You claim authorship for a patch which was written by Marc:
https://lore.kernel.org/all/87sf5x6cdu.wl-maz@kernel.org
without even the courtesy of giving him credit via 'Originally-by' ?
That's not how it works.
Thanks,
tglx
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