Messages in this thread | | | Date | Fri, 27 Oct 2023 19:38:33 +0100 | From | Conor Dooley <> | Subject | Re: [PATCH 1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible |
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On Fri, Oct 27, 2023 at 01:22:36PM -0500, Rob Herring wrote: > On Thu, Oct 26, 2023 at 02:10:37PM +0100, Conor Dooley wrote: > > On Wed, Oct 25, 2023 at 11:56:37AM -0700, Emil Renner Berthing wrote: > > > This cache controller is also used on the StarFive JH7100 SoC. > > > Unfortunately it needs a quirk to work properly, so add dedicated > > > compatible string to be able to match it. > > > > > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Did you want me to pick this up? Or you or Palmer will?
Me or Palmer I guess, I was going to take the lot together through soc.
Cheers, Conor. [unhandled content-type:application/pgp-signature] | |