Messages in this thread | | | Date | Wed, 25 Oct 2023 17:05:18 -0500 | From | Bjorn Helgaas <> | Subject | Re: [PATCH v4 2/2] PCI: altera: add support for agilex family fpga |
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[+cc Joyce]
On Sun, Sep 17, 2023 at 10:35:46PM +0530, sharath.kumar.d.m@intel.com wrote: > From: D M Sharath Kumar <sharath.kumar.d.m@intel.com> > > create new instance of struct altera_pcie_data for > "altr,pcie-root-port-3.0" > provide corresponding callback > "port_conf_off" points to avmm port config register base
Please mention the hardware platform that this corresponds to.
> + /* interrupt pin not programmed in hardware, set to INTA*/
Add space before closing "*/".
> + if (status & AGLX_CFG_AER) { > + ret = generic_handle_domain_irq(pcie->irq_domain, 0); > + if (ret) > + dev_err_ratelimited(dev, "unexpected IRQ\n");
Maybe include a hint about what the unexpected IRQ was? An IRQ number or "status" value?
> +static const struct altera_pcie_ops altera_pcie_ops_3_0 = { > + .alt_read_own_cfg = aglx_read_own_cfg, > + .alt_write_own_cfg = aglx_write_own_cfg, > + .get_link_status = aglx_altera_pcie_link_up, > + .alt_read_other_cfg = aglx_read_other_cfg, > + .alt_write_other_cfg = aglx_write_other_cfg, > + .rp_isr = aglx_isr,
Use the same order of function pointers in all of these structs and make it match the struct altera_pcie_ops definition. (Don't put .get_link_status in the middle of the config accessors.)
> static const struct of_device_id altera_pcie_of_match[] = { > {.compatible = "altr,pcie-root-port-1.0", > .data = &altera_pcie_1_0_data }, > {.compatible = "altr,pcie-root-port-2.0", > .data = &altera_pcie_2_0_data }, > + {.compatible = "altr,pcie-root-port-3.0", > + .data = &altera_pcie_3_0_data },
Make the .data indentation match the rest.
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