Messages in this thread | | | Date | Tue, 24 Oct 2023 14:36:31 -0500 | From | Rob Herring <> | Subject | Re: [PATCH v5 2/3] dt-bindings: clock: si5351: add PLL reset mode property |
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On Fri, 20 Oct 2023 13:34:15 +0200, Alvin Šipraga wrote: > From: Alvin Šipraga <alsi@bang-olufsen.dk> > > For applications where the PLL must be adjusted without glitches in the > clock output(s), a new silabs,pll-reset-mode property is added. It > can be used to specify whether or not the PLL should be reset after > adjustment. Resetting is known to cause glitches. > > For compatibility with older device trees, it must be assumed that the > default PLL reset mode is to unconditionally reset after adjustment. > > Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> > Cc: Rabeeh Khoury <rabeeh@solid-run.com> > Cc: Jacob Siverskog <jacob@teenage.engineering> > Cc: Sergej Sawazki <sergej@taudac.com> > Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk> > --- > .../devicetree/bindings/clock/silabs,si5351.yaml | 24 ++++++++++++++++++++++ > 1 file changed, 24 insertions(+) >
Reviewed-by: Rob Herring <robh@kernel.org>
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