Messages in this thread | | | Date | Sat, 21 Oct 2023 13:53:40 +0200 | From | Sebastian Fricke <> | Subject | Re: [PATCH v13 6/8] media: dt-bindings: wave5: add Chips&Media 521c codec IP support |
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Hello Krzysztof and Rob,
this question is quite important for our next version and for the overall direction of the DT bindings, could you have a look at this?
Thank you and Regards, Sebastian
On 17.10.2023 19:09, Devarsh Thakkar wrote: >Hi Sebastian, Krzysztof, Rob, > >On 12/10/23 16:31, Sebastian Fricke wrote: >> From: Robert Beckett <bob.beckett@collabora.com> >> >> Add bindings for the chips&media wave5 codec driver >> >> Signed-off-by: Robert Beckett <bob.beckett@collabora.com> >> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> >> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> >> --- >> .../devicetree/bindings/media/cnm,wave5.yaml | 60 ++++++++++++++++++++++ >> 1 file changed, 60 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/media/cnm,wave5.yaml b/Documentation/devicetree/bindings/media/cnm,wave5.yaml >> new file mode 100644 >> index 000000000000..b31d34aec05b >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/media/cnm,wave5.yaml >> @@ -0,0 +1,60 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/media/cnm,wave5.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Chips&Media Wave 5 Series multi-standard codec IP >> + >> +maintainers: >> + - Nas Chung <nas.chung@chipsnmedia.com> >> + - Jackson Lee <jackson.lee@chipsnmedia.com> >> + >> +description: >> + The Chips&Media WAVE codec IP is a multi format video encoder/decoder >> + >> +properties: >> + compatible: >> + enum: >> + - cnm,cm521c-vpu >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: VCODEC clock >> + >> + interrupts: >> + maxItems: 1 >> + >> + power-domains: >> + maxItems: 1 >> + >> + resets: >> + maxItems: 1 >> + >> + sram: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: >> + The VPU uses the SRAM to store some of the reference data instead of >> + storing it on DMA memory. It is mainly used for the purpose of reducing >> + bandwidth. >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - interrupts >> + > >Is it possible to keep interrupts property as optional given HW can still work >without it if SW does polling of ISR using registers? > >The reason to ask is in TI AM62A SoC (which also uses this codec) there is an >SoC errata of missing interrupt line to A53 and we are using SW based polling >locally to run the driver. > >We were planning to upstream that SW based polling support patch in CnM driver >once this base initial driver patch series gets merged, but just wanted to >check if upfront it is possible to have interrupts property as optional so >that we don't have to change the binding doc again to make it optional later on. > >Also note that the polling patch won't be specific to AM62A, other SoC's too >which use this wave5 hardware if they want can enable polling by choice (by >removing interrupt property) > >Could you please share your opinion on this ? > >Regards >Devarsh > >> +additionalProperties: false >> + >> +examples: >> + - | >> + vpu: video-codec@12345678 { >> + compatible = "cnm,cm521c-vpu"; >> + reg = <0x12345678 0x1000>; >> + clocks = <&clks 42>; >> + interrupts = <42>; >> + sram = <&sram>; >> + }; >> >_______________________________________________ >Kernel mailing list -- kernel@mailman.collabora.com >To unsubscribe send an email to kernel-leave@mailman.collabora.com
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