Messages in this thread | | | Date | Thu, 19 Oct 2023 14:01:31 +0530 | Subject | Re: [PATCH] arm64: Independently update HDFGRTR_EL2 and HDFGWTR_EL2 | From | Anshuman Khandual <> |
| |
On 10/19/23 12:45, Marc Zyngier wrote: > On Thu, 19 Oct 2023 04:36:15 +0100, > Anshuman Khandual <anshuman.khandual@arm.com> wrote: >> >> >> >> On 10/18/23 18:10, Marc Zyngier wrote: >>> On Wed, 18 Oct 2023 04:00:07 +0100, >>> Anshuman Khandual <anshuman.khandual@arm.com> wrote: >>>> >>>> Currently PMSNEVFR_EL1 system register read, and write access EL2 traps are >>>> disabled, via setting the same bit (i.e 62) in HDFGRTR_EL2, and HDFGWTR_EL2 >>>> respectively. Although very similar, bit fields are not exact same in these >>>> two EL2 trap configure registers particularly when it comes to read-only or >>>> write-only accesses such as ready-only 'HDFGRTR_EL2.nBRBIDR' which needs to >>>> be set while enabling BRBE on NVHE platforms. Using the exact same bit mask >>>> fields for both these trap register risk writing into their RESERVED areas, >>>> which is undesirable. >>> >>> Sorry, I don't understand at all what you are describing. You seem to >>> imply that the read and write effects of the FGT doesn't apply the >>> same way. But my reading of the ARM ARM is that behave completely >>> symmetrically. >>> >>> Also, what is nBRBIDR doing here? It is still set to 0. What >>> 'RESERVED' state are you talking about? >> >> Let's observe the following example which includes the nBRBIDR problem, >> mentioned earlier. >> >> Read access trap configure >> >> HDFGRTR_EL2[59] - nBRBIDR >> HDFGRTR_EL2[58] - PMCEIDn_EL0 >> >> Write access trap configure >> >> HDFGWTR_EL2[59:58] - RES0 >> >> Because BRBIDR_EL1 and PMCEID<N>_EL0 are read only registers they don't >> have corresponding entries in HDFGWTR_EL2 for write trap configuration. >> >> Using the exact same value contained in 'x0' both for HDFGRTR_EL2, and >> HDFGWTR_EL2 will be problematic in case it contains bit fields that are >> available only in one of the registers but not in the other. >> >> If 'x0' contains nBRBIDR being set, it will be okay for HDFGRTR_EL2 but >> might not be okay for HDFGWTR_EL2 where it will get into RESERVED areas. > > None of which matters for this patch. You keep arguing about something > that does not exist in the change you're proposing. > > [...] > >> I should have given more details in the commit message but hope >> you have some context now, but please do let me know if there >> is something still missing. > > What is missing is a useful patch. This one just obfuscates things for > no particular purpose. If you have a useful change to contribute, > please send that instead (your BRBE change). We don't need an extra, > standalone and pointless patch such as this one.
I will fold this patch with other BRBE changes as mentioned earlier but thought that - separating out updates for HDFGRTR_EL2, and HDFGWTR_EL2 should be done as stand alone change in a preparatory patch. Seems like that was an incorrect assumption.
| |