Messages in this thread Patch in this message | | | Date | Wed, 18 Oct 2023 19:51:39 +0200 | Subject | Re: [PATCH v3 6/8] arm64: dts: qcom: ipq5332: populate the opp table based on the eFuse | From | Konrad Dybcio <> |
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On 10/18/23 11:29, Varadarajan Narayanan wrote: > IPQ53xx have different OPPs available for the CPU based on > SoC variant. This can be determined through use of an eFuse > register present in the silicon. > > Add support to read the eFuse and populate the OPPs based on it. > > ------------------------------------------------ > Frequency BIT2 BIT1 opp-supported-hw > 1.1GHz 1.5GHz > ------------------------------------------------ > 1100000000 1 1 0xf BIT(0) | BIT(1) | BIT(2) is 0x7
> 1500000000 0 1 0x3 > ------------------------------------------------ > > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > v2: Fix inconsistencies in comment and move it to commit log > as suggested > Remove opp-microvolt entries as no regulator is managed by Linux > cpu_speed_bin -> cpu-speed-bin in node name > Remove "nvmem-cell-names" due to dtbs_check error > --- > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index 4206f05..a0dcba3 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -91,11 +91,19 @@ > }; > > cpu_opp_table: opp-table-cpu { > - compatible = "operating-points-v2"; > + compatible = "operating-points-v2-kryo-cpu"; > opp-shared; > + nvmem-cells = <&cpu_speed_bin>; > > - opp-1488000000 { > - opp-hz = /bits/ 64 <1488000000>; > + opp-1100000000 { > + opp-hz = /bits/ 64 <1100000000>; > + opp-supported-hw = <0xF>; hex literals must be lowercase.
Konrad
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