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    Subject[PATCH v10 04/50] x86/cpufeatures: Add SEV-SNP CPU feature
    Date
    From: Brijesh Singh <brijesh.singh@amd.com>

    Add CPU feature detection for Secure Encrypted Virtualization with
    Secure Nested Paging. This feature adds a strong memory integrity
    protection to help prevent malicious hypervisor-based attacks like
    data replay, memory re-mapping, and more.

    Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
    Signed-off-by: Jarkko Sakkinen <jarkko@profian.com>
    Signed-off-by: Ashish Kalra <Ashish.Kalra@amd.com>
    Signed-off-by: Michael Roth <michael.roth@amd.com>
    ---
    arch/x86/include/asm/cpufeatures.h | 1 +
    arch/x86/kernel/cpu/amd.c | 5 +++--
    tools/arch/x86/include/asm/cpufeatures.h | 1 +
    3 files changed, 5 insertions(+), 2 deletions(-)

    diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
    index 58cb9495e40f..1640cedd77f1 100644
    --- a/arch/x86/include/asm/cpufeatures.h
    +++ b/arch/x86/include/asm/cpufeatures.h
    @@ -437,6 +437,7 @@
    #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */
    #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */
    #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
    +#define X86_FEATURE_SEV_SNP (19*32+ 4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */
    #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */
    #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */
    #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* AMD SEV-ES full debug state swap support */
    diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
    index dd8379d84445..14ee7f750cc7 100644
    --- a/arch/x86/kernel/cpu/amd.c
    +++ b/arch/x86/kernel/cpu/amd.c
    @@ -630,8 +630,8 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
    * SME feature (set in scattered.c).
    * If the kernel has not enabled SME via any means then
    * don't advertise the SME feature.
    - * For SEV: If BIOS has not enabled SEV then don't advertise the
    - * SEV and SEV_ES feature (set in scattered.c).
    + * For SEV: If BIOS has not enabled SEV then don't advertise SEV and
    + * any additional functionality based on it.
    *
    * In all cases, since support for SME and SEV requires long mode,
    * don't advertise the feature under CONFIG_X86_32.
    @@ -666,6 +666,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
    clear_sev:
    setup_clear_cpu_cap(X86_FEATURE_SEV);
    setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
    + setup_clear_cpu_cap(X86_FEATURE_SEV_SNP);
    }
    }

    diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
    index 798e60b5454b..669f45eefa0c 100644
    --- a/tools/arch/x86/include/asm/cpufeatures.h
    +++ b/tools/arch/x86/include/asm/cpufeatures.h
    @@ -432,6 +432,7 @@
    #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */
    #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */
    #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
    +#define X86_FEATURE_SEV_SNP (19*32+ 4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */
    #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */
    #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */
    #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* AMD SEV-ES full debug state swap support */
    --
    2.25.1
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