Messages in this thread | ![/](/images/icornerl.gif) | | Date | Mon, 16 Oct 2023 13:32:04 -0500 | Subject | Re: [PATCH] x86/mm: fix pg_level_to_pfn for 5-level paging mode. | From | "Kalra, Ashish" <> |
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On 10/14/2023 3:47 AM, Ingo Molnar wrote: > > * Ashish Kalra <Ashish.Kalra@amd.com> wrote: > >> From: Ashish Kalra <ashish.kalra@amd.com> >> >> Add support for 5-level paging in pg_level_to_pfn(). >> >> Signed-off-by: Ashish Kalra <ashish.kalra@amd.com> >> --- >> arch/x86/mm/mem_encrypt_amd.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c >> index 6faea41e99b6..45914568596a 100644 >> --- a/arch/x86/mm/mem_encrypt_amd.c >> +++ b/arch/x86/mm/mem_encrypt_amd.c >> @@ -267,6 +267,10 @@ static unsigned long pg_level_to_pfn(int level, pte_t *kpte, pgprot_t *ret_prot) >> pfn = pud_pfn(*(pud_t *)kpte); >> prot = pud_pgprot(*(pud_t *)kpte); >> break; >> + case PG_LEVEL_512G: >> + pfn = p4d_pfn(*(p4d_t *)kpte); >> + prot = p4d_pgprot(*(p4d_t *)kpte); >> + break; > > Mind explaining what happens if we don't have this fix, how you found it, > which users are expected to be affected by it, whether that's the full > known extent of 5-level paging support deficiencies in mem_encrypt_amd.c,foud > etc? >
It was found during working on SNP guest kexec support, this helper function is used during early boot stage for setting of C-bit on the PTEs and additionally need this same helper for switching shared pages to private during guest kexec, so i believe this patch is needed.
Thanks, Ashish
> In addition to such patches being much easier on the eyes, it also helps > maintainers prioritize patches. > > Thanks, > > Ingo >
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