Messages in this thread | | | From | Miguel Luis <> | Subject | Re: [PATCH v3 3/3] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization | Date | Fri, 13 Oct 2023 18:41:42 +0000 |
| |
Hi Eric,
> On 12 Oct 2023, at 15:22, Eric Auger <eric.auger@redhat.com> wrote: > > Hi Miguel, > > On 10/11/23 20:01, Miguel Luis wrote: >> Implement a fine grained approach in the _EL2 sysreg ranges. >> >> Fixes: d0fc0a2519a6 ("KVM: arm64: nv: Add trap forwarding for HCR_EL2") >> Signed-off-by: Miguel Luis <miguel.luis@oracle.com> >> --- >> arch/arm64/kvm/emulate-nested.c | 88 ++++++++++++++++++++++++++++++--- >> 1 file changed, 82 insertions(+), 6 deletions(-) >> >> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c >> index 9ced1bf0c2b7..3af49e130ee6 100644 >> --- a/arch/arm64/kvm/emulate-nested.c >> +++ b/arch/arm64/kvm/emulate-nested.c >> @@ -648,15 +648,91 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { >> SR_TRAP(SYS_APGAKEYLO_EL1, CGT_HCR_APK), >> SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK), >> /* All _EL2 registers */ >> - SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0), >> - sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV), >> + SR_TRAP(SYS_VPIDR_EL2, CGT_HCR_NV), > I think you miss DBGVCR32_EL2
That would be op0 == 10, which I indeed didn't considered given the ranges previously defined. From its pseudocode I see it would make sense only if EL1 would support AArch32 but that seems not to be in the plans.
>> + SR_TRAP(SYS_VMPIDR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_SCTLR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ACTLR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_SCTLR2_EL2, CGT_HCR_NV), >> + SR_RANGE_TRAP(SYS_HCR_EL2, >> + SYS_HCRX_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_SMPRIMAP_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_SMCR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_SDER32_EL2, CGT_HCR_NV), >> + SR_RANGE_TRAP(SYS_TTBR0_EL2, >> + SYS_TCR2_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_VTTBR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_VTCR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_VNCR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_VSTTBR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_VSTCR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_DACR32_EL2, CGT_HCR_NV), >> + SR_RANGE_TRAP(SYS_HDFGRTR_EL2, >> + SYS_HAFGRTR_EL2, CGT_HCR_NV), >> /* Skip the SP_EL1 encoding... */ >> SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV), >> SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV), >> - SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1), >> - sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV), >> - SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0), >> - sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV), >> + /* SPSR_irq, SPSR_abt, SPSR_und, SPSR_fiq */ >> + SR_RANGE_TRAP(sys_reg(3, 4, 4, 3, 0), >> + sys_reg(3, 4, 4, 3, 3), CGT_HCR_NV), >> + SR_TRAP(SYS_IFSR32_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_AFSR0_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_AFSR1_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ESR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_VSESR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_FPEXC32_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_TFSR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_FAR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_HPFAR_EL2, CGT_HCR_NV), > you miss BRBCR_EL2
Yes, definitely. Same as above, didn't considered op0 == 10, (Table D18-1). This one seems to me the only one missing too.
>> + SR_TRAP(SYS_PMSCR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_MAIR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_AMAIR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_MPAMHCR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_MPAMVPMV_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_MPAM2_EL2, CGT_HCR_NV), >> + SR_RANGE_TRAP(SYS_MPAMVPM0_EL2, >> + SYS_MPAMVPM7_EL2, CGT_HCR_NV), > About the MPAM where did you find the pseudo code?
The pseucode isn't available on the document. I'm following the statement when HCR_EL2.NV is 1, where:
"The System or Special-purpose registers for which accesses are trapped and reported using EC syndrome value 0x18 are as follows: — Registers accessed using MRS or MSR with a name ending in _EL2, except, [...]"
>> + /* >> + * Note that the spec. describes a group of MEC registers >> + * whose access should not trap, therefore skip the following: >> + * MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2, >> + * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2, >> + * VMECID_P_EL2. >> + */ >> + SR_RANGE_TRAP(SYS_VBAR_EL2, >> + SYS_RMR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_VDISR_EL2, CGT_HCR_NV), >> + /* ICH_AP0R<m>_EL2 */ >> + SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2, >> + SYS_ICH_AP0R3_EL2, CGT_HCR_NV), >> + /* ICH_AP1R<m>_EL2 */ >> + SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2, >> + SYS_ICH_AP1R3_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICC_SRE_EL2, CGT_HCR_NV), >> + SR_RANGE_TRAP(SYS_ICH_HCR_EL2, >> + SYS_ICH_EISR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_ELRSR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_VMCR_EL2, CGT_HCR_NV), >> + /* ICH_LR<m>_EL2 */ >> + SR_RANGE_TRAP(SYS_ICH_LR0_EL2, >> + SYS_ICH_LR15_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_CONTEXTIDR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_TPIDR_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_SCXTNUM_EL2, CGT_HCR_NV), >> + /* AMEVCNTVOFF0<n>_EL2, AMEVCNTVOFF1<n>_EL2 */ >> + SR_RANGE_TRAP(SYS_AMEVCNTVOFF0n_EL2(0), >> + SYS_AMEVCNTVOFF1n_EL2(15), CGT_HCR_NV), >> + /* CNT*_EL2 */ >> + SR_TRAP(SYS_CNTVOFF_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_CNTPOFF_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_CNTHCTL_EL2, CGT_HCR_NV), >> + SR_RANGE_TRAP(SYS_CNTHP_TVAL_EL2, >> + SYS_CNTHP_CVAL_EL2, CGT_HCR_NV), >> + SR_RANGE_TRAP(SYS_CNTHV_TVAL_EL2, >> + SYS_CNTHV_CVAL_EL2, CGT_HCR_NV), >> + SR_RANGE_TRAP(SYS_CNTHVS_TVAL_EL2, >> + SYS_CNTHVS_CVAL_EL2, CGT_HCR_NV), >> + SR_RANGE_TRAP(SYS_CNTHPS_TVAL_EL2, >> + SYS_CNTHPS_CVAL_EL2, CGT_HCR_NV), >> /* All _EL02, _EL12 registers */ >> SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0), >> sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV), > Besides this looks good to me and to me this looks safer than the > previous large span approach but that's my taste ;-) >
Your suggestions made total sense to me.
Thanks! Miguel
> Thanks > > Eric
| |