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    Subject[PATCH V2 1/4] dt-bindings: clock: add Amlogic C3 PLL clock controller bindings
    Date
    Add the C3 PLL clock controller dt-bindings for Amlogic C3 SoC family

    Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
    ---
    V1 -> V2: Fix errors when check dtbinding use "make dt_binding_check"
    ---
    .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 +++++++++++++++++++
    .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 42 +++++++++++++
    2 files changed, 101 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
    create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h

    diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
    new file mode 100644
    index 000000000000..a646992917b7
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
    @@ -0,0 +1,59 @@
    +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    +# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
    +%YAML 1.2
    +---
    +$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
    +$schema: http://devicetree.org/meta-schemas/core.yaml#
    +
    +title: Amlogic C3 serials PLL Clock Controller
    +
    +maintainers:
    + - Chuan Liu <chuan.liu@amlogic.com>
    +
    +properties:
    + compatible:
    + const: amlogic,c3-pll-clkc
    +
    + reg:
    + maxItems: 1
    +
    + clocks:
    + minItems: 1
    + items:
    + - description: input pll_in
    + - description: input mclk_pll_in
    +
    + clock-names:
    + minItems: 1
    + items:
    + - const: pll_in
    + - const: mclk_pll_in
    +
    + "#clock-cells":
    + const: 1
    +
    +required:
    + - compatible
    + - reg
    + - clocks
    + - clock-names
    + - "#clock-cells"
    +
    +additionalProperties: false
    +
    +examples:
    + - |
    + #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
    + apb {
    + #address-cells = <2>;
    + #size-cells = <2>;
    +
    + clkc_pll: clock-controller@8000 {
    + compatible = "amlogic,c3-pll-clkc";
    + reg = <0x0 0x8000 0x0 0x1a4>;
    + clocks = <&clkc_periphs CLKID_PLL_IN>,
    + <&clkc_periphs CLKID_MCLK_PLL_IN>;
    + clock-names = "pll_in", "mclk_pll_in";
    + #clock-cells = <1>;
    + };
    + };
    diff --git a/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
    new file mode 100644
    index 000000000000..aa731e8fae29
    --- /dev/null
    +++ b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
    @@ -0,0 +1,42 @@
    +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
    +/*
    + * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
    + * Author: Chuan Liu <chuan.liu@amlogic.com>
    + */
    +
    +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
    +#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
    +
    +#define CLKID_FIXED_PLL_DCO 0
    +#define CLKID_FIXED_PLL 1
    +#define CLKID_FCLK_DIV40_DIV 2
    +#define CLKID_FCLK_DIV40 3
    +#define CLKID_FCLK_DIV2_DIV 4
    +#define CLKID_FCLK_DIV2 5
    +#define CLKID_FCLK_DIV2P5_DIV 6
    +#define CLKID_FCLK_DIV2P5 7
    +#define CLKID_FCLK_DIV3_DIV 8
    +#define CLKID_FCLK_DIV3 9
    +#define CLKID_FCLK_DIV4_DIV 10
    +#define CLKID_FCLK_DIV4 11
    +#define CLKID_FCLK_DIV5_DIV 12
    +#define CLKID_FCLK_DIV5 13
    +#define CLKID_FCLK_DIV7_DIV 14
    +#define CLKID_FCLK_DIV7 15
    +#define CLKID_GP0_PLL_DCO 16
    +#define CLKID_GP0_PLL 17
    +#define CLKID_HIFI_PLL_DCO 18
    +#define CLKID_HIFI_PLL 19
    +#define CLKID_MCLK_PLL_DCO 20
    +#define CLKID_MCLK_PLL 21
    +#define CLKID_MCLK_PLL_CLK 22
    +#define CLKID_MCLK0_SEL 23
    +#define CLKID_MCLK0_SEL_OUT 24
    +#define CLKID_MCLK0_DIV 25
    +#define CLKID_MCLK0 26
    +#define CLKID_MCLK1_SEL 27
    +#define CLKID_MCLK1_SEL_OUT 28
    +#define CLKID_MCLK1_DIV 29
    +#define CLKID_MCLK1 30
    +
    +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */
    base-commit: 57b55c76aaf1ba50ecc6dcee5cd6843dc4d85239
    --
    2.37.1

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