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    Subject[PATCH v5 7/9] arm64: dts : ti: k3-am68-sk-som: Add DDR carveout memory nodes for C71x DSP
    Date
    Two carveout reserved memory nodes each have been added for each of the
    C71x DSP for the TI K3 AM68 SK boards. These nodes are assigned to the
    respective rproc device nodes as well. The first region will be used as
    the DMA pool for the rproc device, and the second region will furnish
    the static carveout regions for the firmware memory.

    The current carveout addresses and sizes are defined statically for each
    device. The C71x DSP processor supports a MMU called CMMU, but is not
    currently supported and as such requires the exact memory used by the
    firmware to be set-aside.

    Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
    Signed-off-by: Apurva Nandan <a-nandan@ti.com>
    Reviewed-by: Udit Kumar <u-kumar1@ti.com>
    ---
    arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 52 ++++++++++++++++++++++
    1 file changed, 52 insertions(+)

    diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
    index beab405274ab..20861a0a46b0 100644
    --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
    +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
    @@ -98,6 +98,30 @@ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
    no-map;
    };

    + c71_0_dma_memory_region: c71-dma-memory@a6000000 {
    + compatible = "shared-dma-pool";
    + reg = <0x00 0xa6000000 0x00 0x100000>;
    + no-map;
    + };
    +
    + c71_0_memory_region: c71-memory@a6100000 {
    + compatible = "shared-dma-pool";
    + reg = <0x00 0xa6100000 0x00 0xf00000>;
    + no-map;
    + };
    +
    + c71_1_dma_memory_region: c71-dma-memory@a7000000 {
    + compatible = "shared-dma-pool";
    + reg = <0x00 0xa7000000 0x00 0x100000>;
    + no-map;
    + };
    +
    + c71_1_memory_region: c71-memory@a7100000 {
    + compatible = "shared-dma-pool";
    + reg = <0x00 0xa7100000 0x00 0xf00000>;
    + no-map;
    + };
    +
    rtos_ipc_memory_region: ipc-memories@a8000000 {
    reg = <0x00 0xa8000000 0x00 0x01c00000>;
    alignment = <0x1000>;
    @@ -170,6 +194,20 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
    };
    };

    +&mailbox0_cluster4 {
    + status = "okay";
    + interrupts = <420>;
    + mbox_c71_0: mbox-c71-0 {
    + ti,mbox-rx = <0 0 0>;
    + ti,mbox-tx = <1 0 0>;
    + };
    +
    + mbox_c71_1: mbox-c71-1 {
    + ti,mbox-rx = <2 0 0>;
    + ti,mbox-tx = <3 0 0>;
    + };
    +};
    +
    &mcu_r5fss0_core0 {
    mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
    memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
    @@ -205,3 +243,17 @@ &main_r5fss1_core1 {
    memory-region = <&main_r5fss1_core1_dma_memory_region>,
    <&main_r5fss1_core1_memory_region>;
    };
    +
    +&c71_0 {
    + status = "okay";
    + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
    + memory-region = <&c71_0_dma_memory_region>,
    + <&c71_0_memory_region>;
    +};
    +
    +&c71_1 {
    + status = "okay";
    + mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
    + memory-region = <&c71_1_dma_memory_region>,
    + <&c71_1_memory_region>;
    +};
    --
    2.34.1
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