Messages in this thread | | | Date | Thu, 5 Jan 2023 13:59:27 -0500 | Subject | Re: [PATCH net-next v5 4/4] phy: aquantia: Determine rate adaptation support from registers | From | Sean Anderson <> |
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On 1/5/23 13:55, Russell King (Oracle) wrote: > On Thu, Jan 05, 2023 at 07:52:06PM +0200, Vladimir Oltean wrote: >> On Thu, Jan 05, 2023 at 12:43:47PM -0500, Sean Anderson wrote: >> > Again, this is to comply with the existing API assumptions. The current >> > code is buggy. Of course, another way around this is to modify the API. >> > I have chosen this route because I don't have a situation like you >> > described. But if support for that is important to you, I encourage you >> > to refactor things. >> >> I don't think I'm aware of a practical situation like that either. >> I remember seeing some S32G boards with Aquantia PHYs which use 2500BASE-X >> for 2.5G and SGMII for <=1G, but that's about it in terms of protocol switching. > > 88x3310 can dynamically switch between 10GBASE-R, 5GBASE-R, 2500BASE-X > and SGMII if rate adaption is not being used (and the rate adaption > method it supports in non-MACSEC PHYs is only via increasing the IPG on > the MAC... which currently no MAC driver supports.) >
As an aside, do you know of any MACs which support open-loop rate matching to below ~95% of the line rate (the amount necessary for 10GBASE-W)?
--Sean
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