Messages in this thread | ![/](/images/icornerl.gif) | | Date | Wed, 4 Jan 2023 12:18:28 +0000 | From | Conor Dooley <> | Subject | Re: [PATCH] riscv: Move call to init_cpu_topology() to later initialization stage |
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Hey Sudeep,
On Wed, Jan 04, 2023 at 10:49:00AM +0000, Sudeep Holla wrote: > On Wed, Jan 04, 2023 at 09:49:48AM +0000, Conor Dooley wrote: > > [...] > > > >> Uhh, so where did this "capacity-dmips-mhz" property actually come from? > > >> I had a quick check of qemu with grep & I don't see anything there that > > >> would add this property. > > >> This property should not be valid on anything other than arm AFAICT. > > > > > >This DT parameter is not in default Qemu. I've added it for testing (see test steps in below). > > >This is preparation to support asymmetric CPU topology for RISC-V. > > > > The property is only valid on arm, so how does arm64 deal with such > > asymmetric topologies without it? > > I don't think we can deal with asymmetric topologies without this. > Yes we can detect the difference in the CPU types but we can only assume > there are symmetric in terms of performance in absence of this property.
I looked at the bindings for it and forgot that the arm directory of bindings applies to both arm and arm64. I see now that it is also used on arm64.
> > > Why should we "fix" something that may never be a valid dts? > > > > I would not say invalid. But surely absence of it must be handled and > we do that for sure. IIRC, here the presence of it is causing the issue. > And if it is present means someone is trying to build it(I do understand > this is Qemu but is quite common these days for power and performance > balance in many SoC)
I said "invalid" as the binding is defined for arm{,64} in arm/cpus.yaml & documented in the same directory in cpu-capacity.txt, but not yet on riscv. All bets are off if your cpu node is using invalid properties IMO, at least this one will fail to boot!
However, I see no reason (at this point) that we should deviate from what arm{,64} is doing & that documenation should probably move to a shared location at some point.
> > >> > > >> I know arm64 does this, but there is any real reason for us to do so? > > >> @Sudeep, do you know why arm64 calls that each time? > > > > I got myself mixed up between places I fiddled with storing the topology, so you can ignore that question Sudeep. > > Clearly it's the one in smp_callin() that gets called for each CPU. > > Woops. > > > > Hmm I should have read all the messages in the thread. Doing by date/time > didn't work well for me 😄.
Meh, my fault for getting confused ;)
> > >> Or if it is worth "saving" that call on riscv, since arm64 is clearly happily calling > > >> it for many years & calling it later would likely head off a good few allocation > > >> issues (like the one we saw with the topology reworking a few months ago). > > > > ...but is it still worth moving the function call later to head off any allocation failures if core topology code changes? > > > > Agreed, given how we faced similar issues with cacheinfo on few RISC-V > platforms.
Sweet, sounds like a plan to me. I'll go suggest some commit message re-wording I think.
Thanks Sudeep!
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