Messages in this thread | | | Date | Mon, 2 Jan 2023 11:38:34 +0100 | From | Marijn Suijten <> | Subject | Re: [RFC PATCH 5/7] drm/msm/dpu: Document and enable TEAR interrupts on DSI interfaces |
| |
On 2023-01-01 15:12:35, Dmitry Baryshkov wrote: > On 31/12/2022 23:50, Marijn Suijten wrote: > > <snip> > > -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \ > > +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit, _tear_reg, _tear_rd_ptr_bit) \ > > {\ > > .name = _name, .id = _id, \ > > - .base = _base, .len = 0x280, \ > > + .base = _base, .len = _len, \ > > Please move .len setting to a separate patch, it is not direclty related > to tear interrupt addition.
It is directly related in that the TE registers reside in the extra space beyond 0x280, but I can surely make that explicit in a separate patch.
> > .features = _features, \ > > .type = _type, \ > > .controller_id = _ctrl_id, \ > > .prog_fetch_lines_worst_case = _progfetch, \ > > .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \ > > .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \ > > + .intr_tear_rd_ptr = DPU_IRQ_IDX(_tear_reg, _tear_rd_ptr_bit), \ > > Initially I added separate _reg and _bit settings because reg was common > to both interrupts. However now as tear interrups use different reg it > might be better to first move DPU_IRQ_IDX out of this macro () and then > to add your tear_rd_ptr_intr as a single intr_idx.
I assumed as much; then we do get the duplication of _reg but I guess it's not too bad if the lines are nicely wrapped like in _pp[]. I'll do so in a separate patch.
- Marijn
<snip>
| |