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    SubjectRe: [PATCH v10 02/21] dt-bindings: mediatek,dp: Add Display Port binding
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    On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote:
    > From: Markus Schneider-Pargmann <msp@baylibre.com>
    >
    > This controller is present on several mediatek hardware. Currently
    > mt8195 and mt8395 have this controller without a functional
    > difference,
    > so only one compatible field is added.
    >
    > The controller can have two forms, as a normal display port and as an
    > embedded display port.
    >
    > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
    > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
    > ---
    > .../display/mediatek/mediatek,dp.yaml | 99
    > +++++++++++++++++++
    > 1 file changed, 99 insertions(+)
    > create mode 100644
    > Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
    >
    > diff --git
    > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
    > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
    > new file mode 100644
    > index 000000000000..36ae0a6df299
    > --- /dev/null
    > +++
    > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
    > @@ -0,0 +1,99 @@
    > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    > +%YAML 1.2
    > +---
    > +$id:
    > http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
    > +$schema: http://devicetree.org/meta-schemas/core.yaml#
    > +
    > +title: MediaTek Display Port Controller
    > +
    > +maintainers:
    > + - CK Hu <ck.hu@mediatek.com>
    > + - Jitao shi <jitao.shi@mediatek.com>
    > +
    > +description: |
    > + Device tree bindings for the MediaTek (embedded) Display Port
    > controller
    > + present on some MediaTek SoCs.
    > +
    > +properties:
    > + compatible:
    > + enum:
    > + - mediatek,mt8195-dp-tx
    > +
    > + reg:
    > + maxItems: 1
    > +
    > + interrupts:
    > + maxItems: 1
    > +
    > + clocks:
    > + items:
    > + - description: faxi clock
    > +
    > + clock-names:
    > + items:
    > + - const: faxi
    > +
    > + power-domains:
    > + maxItems: 1
    > +
    > + ports:
    > + $ref: /schemas/graph.yaml#/properties/ports
    > + properties:
    > + port@0:
    > + $ref: /schemas/graph.yaml#/properties/port
    > + description: Input endpoint of the controller, usually
    > dp_intf
    > +
    > + port@1:
    > + $ref: /schemas/graph.yaml#/properties/port
    > + description: Output endpoint of the controller
    > +
    > + max-lanes:
    > + maxItems: 1
    > + description: maximum number of lanes supported by the hardware
    > +
    > + max-linkrate:
    > + maxItems: 1
    > + description: maximum link rate supported by the hardware
    > +
    > +required:
    > + - compatible
    > + - reg
    > + - interrupts
    > + - ports
    > + - max-lanes
    > + - max-linkrate
    > +
    > +additionalProperties: false
    > +
    > +examples:
    > + - |
    > + #include <dt-bindings/interrupt-controller/arm-gic.h>
    > + #include <dt-bindings/power/mt8195-power.h>
    > + edp_tx: edp_tx@1c500000 {
    'edp_tx: ' can be removed

    > + compatible = "mediatek,mt8195-dp-tx";
    > + reg = <0 0x1c500000 0 0x8000>;
    reg = <0x1c500000 0x8000>;
    #address-cells, #size-cells are both 1 by default

    > + interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
    > + power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
    > + pinctrl-names = "default";
    > + pinctrl-0 = <&edp_pin>;
    > + max-lanes = /bits/ 8 <4>;
    > + max-linkrate = /bits/ 8 <0x1e>;
    > +
    > + ports {
    > + #address-cells = <1>;
    > + #size-cells = <0>;
    > +
    > + port@0 {
    > + reg = <0>;
    > + edp_in: endpoint {
    > + remote-endpoint = <&dp_intf0_out>;
    > + };
    > + };
    > + port@1 {
    > + reg = <1>;
    > + edp_out: endpoint {
    > + remote-endpoint = <&panel_in>;
    > + };
    > + };
    > + };
    > + };

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