Messages in this thread Patch in this message | | | From | Piyush Mehta <> | Subject | RE: [PATCH] usb: chipidea: udc: make controller hardware endpoint primed | Date | Mon, 13 Sep 2021 09:49:24 +0000 |
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Hello Peter,
Thanks for the review. Please find my inline comment with tag [Piyush].
Regards, Piyush Mehta
-----Original Message----- From: Peter Chen <peter.chen@kernel.org> Sent: Sunday, September 12, 2021 1:11 PM To: Piyush Mehta <piyushm@xilinx.com> Cc: gregkh@linuxfoundation.org; linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; git <git@xilinx.com>; Srinivas Goud <sgoud@xilinx.com>; Michal Simek <michals@xilinx.com> Subject: Re: [PATCH] usb: chipidea: udc: make controller hardware endpoint primed
On 21-09-08 14:13:21, Piyush Mehta wrote: > Root-cause: > There is an issue like endpoint is not recognized as primed, when bus > have more pressure and the add dTD tripwire semaphore (ATDTW bit in > USBCMD register) that can cause the controller to ignore a dTD that is > added to a primed endpoint. > This issue observed with the Windows10 host machine. > > Workaround: > The software must implement a periodic cycle, and check for each dTD, > if the endpoint is primed. It can do this by reading the corresponding > bits in the ENDPTPRIME and ENDPTSTAT registers. If these bits are read > at 0, the software needs to re-prime the endpoint by writing 1 to the > corresponding bit in the ENDPTPRIME register. > > Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> > --- > drivers/usb/chipidea/udc.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c > index 8834ca6..d970f45 100644 > --- a/drivers/usb/chipidea/udc.c > +++ b/drivers/usb/chipidea/udc.c > @@ -49,6 +49,8 @@ ctrl_endpt_in_desc = { > .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX), }; > > +static int reprime_dtd(struct ci_hdrc *ci, struct ci_hw_ep *hwep, > + struct td_node *node); > /** > * hw_ep_bit: calculates the bit number > * @num: endpoint number > @@ -599,8 +601,15 @@ static int _hardware_enqueue(struct ci_hw_ep > *hwep, struct ci_hw_req *hwreq) > > prevlastnode->ptr->next = cpu_to_le32(next); > wmb(); > + > + if (ci->rev == CI_REVISION_22) { > + if (!hw_read(ci, OP_ENDPTSTAT, BIT(n))) > + reprime_dtd(ci, hwep, prevlastnode); > + } > +
Only for version 2.2? [Piyush] Yes, Xilinx chip-idea controller support revision 2.20 only. This solution is validated on revision 2.20 on the zynq7000 platform.
> if (hw_read(ci, OP_ENDPTPRIME, BIT(n))) > goto done; > +
No blank line.
> do { > hw_write(ci, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW); > tmp_stat = hw_read(ci, OP_ENDPTSTAT, BIT(n)); > -- > 2.7.4 >
--
Thanks, Peter Chen
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