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SubjectRe: [PATCH v2 4/4] spi: amd: Don't wait for a write-only transfer to finish
On Fri, Sep 10, 2021 at 12:15:29PM +0100, Lucas Tanure wrote:
> Return from a write-only transfer without waiting for
> it to finish
> But wait before a new transfer as the previous may
> still happening and also wait before reading the data
> from the FIFO
>
> Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
> ---
> -static void amd_spi_execute_opcode(struct amd_spi *amd_spi)
> +static int amd_spi_execute_opcode(struct amd_spi *amd_spi)
> {
> + int ret;
> +
> + ret = amd_spi_busy_wait(amd_spi);
> + if (ret)
> + return ret;
> +
> /* Set ExecuteOpCode bit in the CTRL0 register */
> amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, AMD_SPI_EXEC_CMD);
> - amd_spi_busy_wait(amd_spi);
> +
> + return 0;
> }
>
> static int amd_spi_master_setup(struct spi_device *spi)
> @@ -178,6 +185,7 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
> amd_spi_clear_fifo_ptr(amd_spi);
> /* Execute command */
> amd_spi_execute_opcode(amd_spi);
> + amd_spi_busy_wait(amd_spi);

Surely the previous transfer can't still be happening if this if
unconditional? Should this not be gated on rx_len?

Thanks,
Charles

> /* Read data from FIFO to receive buffer */
> for (i = 0; i < rx_len; i++)
> buf[i] = amd_spi_readreg8(amd_spi, AMD_SPI_FIFO_BASE + tx_len + i);
> --
> 2.33.0
>

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