Messages in this thread | | | From | Rob Herring <> | Date | Mon, 19 Apr 2021 14:00:17 -0500 | Subject | Re: [PATCH v6 02/10] arm64: perf: Enable PMU counter direct access for perf event |
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On Mon, Apr 19, 2021 at 11:14 AM Will Deacon <will@kernel.org> wrote: > > On Thu, Apr 08, 2021 at 01:38:17PM -0500, Rob Herring wrote: > > On Thu, Apr 8, 2021 at 6:08 AM Mark Rutland <mark.rutland@arm.com> wrote: > > > On Wed, Apr 07, 2021 at 01:44:37PM +0100, Will Deacon wrote: > > > > On Thu, Apr 01, 2021 at 02:45:21PM -0500, Rob Herring wrote: > > > > > On Wed, Mar 31, 2021 at 11:01 AM Will Deacon <will@kernel.org> wrote: > > > > I guess I'm just worried about exposing the counters to userspace after > > > > the PMU driver (or perf core?) thinks that they're no longer exposed in > > > > case we leak other events. > > > > > > IMO that's not practically different from the single-PMU case (i.e. > > > multi-PMU isn't material, either we have a concern with leaking or we > > > don't); more on that below. > > Well, maybe. It looks the single-PMU case is exposed to the same issue, > but I think a solution needs to take into account the multi-PMU situation. > > > > While it looks odd to place this on the mm, I don't think it's the end > > > of the world. > > > > > > > However, I'm not sure how this is supposed to work normally: what > > > > happens if e.g. a privileged user has a per-cpu counter for a kernel > > > > event while a task has a counter with direct access -- can that task > > > > read the kernel event out of the PMU registers from userspace? > > > > > > Yes -- userspace could go read any counters even though it isn't > > > supposed to, and could potentially infer information from those. It > > > won't have access to the config registers or kernel data structures, so > > > it isn't guaranteed to know what the even is or when it is > > > context-switched/reprogrammed/etc. > > > > > > If we believe that's a problem, then it's difficult to do anything > > > robust other than denying userspace access entirely, since disabling > > > userspace access while in use would surprise applications, and denying > > > privileged events would need some global state that we consult at event > > > creation time (in addition to being an inversion of privilege). > > > > > > IIRC there was some fuss about this a while back on x86; I'll go dig and > > > see what I can find, unless Peter has a memory... > > > > Maybe this one[1]. > > > > Rob > > > > [1] https://lore.kernel.org/lkml/20200730123815.18518-1-kan.liang@linux.intel.com/ > > Going through the archives and talking to Peter, it looks like this is still > an active area of concern: > > - There are patches to clear "dirty" counters on context-switch. They were > queued for 5.13 but broke -tip on Friday: > > https://lore.kernel.org/lkml/YHm%2FM4za2LpRYePw@hirez.programming.kicks-ass.net/
Yes, nice timing. I've reworked the arm64 support to do the same things (minus the breakage). And it looks like we can simplify things a bit by moving all the context switch handling into .sched_task() and out of switch_mm. Unless there's some case where that wouldn't work that I'm not aware of (entirely likely).
> - Per-cpu events cannot be protected in software: > > https://lore.kernel.org/lkml/CALCETrVVPzUd_hQ8xoomHn_wWRQJUvROeCt2do4_D4ROZoAVMg@mail.gmail.com/ > > so without hardware support, we need a way to disable user access for > people that care about this leakage > > x86 has an "rdpmc" file exposed for the PMU device in sysfs which allows > access to be disabled. I don't think these patches add such a thing, and > that's where the fun with multi-PMU machines would come into play.
The fun is because sysfs will end up with multiple 'rdpmc' files or something else?
Rob
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