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    SubjectRe: [PATCH v2 0/1] arm: topology: parse the topology from the dt
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    On 16/04/2021 11:32, Valentin Schneider wrote:
    > On 16/04/21 15:47, Ruifeng Zhang wrote:
    >> For more requirements, if all cores in one physical cluster, the
    >> {aff2} of all cores are the same value.
    >> i.e. the sc9863a,
    >> core0: 0000000081000000
    >> core1: 0000000081000100
    >> core2: 0000000081000200
    >> core3: 0000000081000300
    >> core4: 0000000081000400
    >> core5: 0000000081000500
    >> core6: 0000000081000600
    >> core7: 0000000081000700
    >>
    >> According to MPIDR all cores will parse to the one cluster, but it's
    >> the big.LITTLE system, it's need two logic cluster for schedule or
    >> cpufreq.
    >> So I think it's better to add the logic of parse topology from DT.
    >
    > Ah, so it's a slightly different issue, but still one that requires a
    > different means of specifying topology.

    I'm confused. Do you have the MT bit set to 1 then? So the issue that
    the mpidr handling in arm32's store_cpu_topology() is not correct does
    not exist?

    With DynamIQ you have only *one* cluster, you should also be able to run
    your big.LITTLE system with only an MC sched domain.

    # cat /proc/schedstat
    cpu0 ....
    domain0 ff ... <- MC
    ...

    You can introduce a cpu-map to create what we called Phantom Domains in
    Android products.

    # cat /proc/schedstat

    cpu0 ....
    domain0 0f ... <- MC
    domain1 ff ... < DIE

    Is this what you need for your arm32 kernel system? Adding the
    possibility to parse cpu-map to create Phantom Domains?

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