Messages in this thread | | | Subject | Re: [PATCH v4 1/7] x86: clk: clk-fch: Add support for newer family of AMD's SOC | From | Stephen Boyd <> | Date | Thu, 09 Dec 2021 17:45:46 -0800 |
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Quoting Limonciello, Mario (2021-11-30 11:41:30) > On 11/25/2021 05:04, Ajit Kumar Pandey wrote: > > @@ -26,22 +27,37 @@ > > #define ST_CLK_GATE 3 > > #define ST_MAX_CLKS 4 > > > > -#define RV_CLK_48M 0 > > -#define RV_CLK_GATE 1 > > -#define RV_MAX_CLKS 2 > > +#define CLK_48M_FIXED 0 > > +#define CLK_GATE_FIXED 1 > > +#define CLK_MAX_FIXED 2 > > + > > +/* List of supported CPU ids for fixed clk */ > > +#define AMD_CPU_ID_RV 0x15D0 > > > > static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" }; > > static struct clk_hw *hws[ST_MAX_CLKS]; > > > > +static const struct pci_device_id soc_pci_ids[] = { > > + { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) }, > > + { } > > +}; > > + > > Have you considered inverting it? The number of ASICs using the "older" > design with the mux and multiple clock sources is a fixed value, but > we'll keep adding new ASICs in the "new" design of just 48Mhz. > > Notably; I see that this series is missing the Yellow Carp ID for > example. We'll keep having more designs with the 48Mhz that need to be > added to this list.
+1 Let's not keep adding to a list.
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