Messages in this thread | | | Date | Mon, 6 Dec 2021 20:35:19 -0800 | From | Vamsi Krishna Lanka <> | Subject | Re: [PATCH v6 2/5] clk: qcom: Add LUCID_EVO PLL type for SDX65 |
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On Thu, Dec 02, 2021 at 04:18:43PM -0800, Stephen Boyd wrote: > Quoting quic_vamslank@quicinc.com (2021-12-01 16:21:32) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > > index eaedcceb766f..e0c67b76d8ac 100644 > > --- a/drivers/clk/qcom/clk-alpha-pll.c > > +++ b/drivers/clk/qcom/clk-alpha-pll.c > > @@ -1741,35 +1760,47 @@ static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, > > LUCID_5LPE_ALPHA_PLL_ACK_LATCH); > > } > > > > +static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, > > + unsigned long parent_rate, unsigned long enable_vote_run) > > +{ > > + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); > > + struct regmap *regmap = pll->clkr.regmap; > > What's going on with the tabbing here?
Yes, actually i used a tab instead of space here. I will correct it.
> > > + int i, val = 0, div, ret; > > Do we need to initialize to 0?
Not needed. Will remove.
> > > + u32 mask; > > + > > + /* > > + * If the PLL is in FSM mode, then treat set_rate callback as a > > + * no-operation. > > + */ > > + ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); > > + if (ret) > > + return ret; > > + > > + if (val & enable_vote_run) > > + return 0; > > + > > + if (!pll->post_div_table) { > > + pr_err("Missing the post_div_table for the PLL\n"); > > Probably useful to know which PLL is missing a table here.
I think that's a good idea on returning which PLL is missing a table.
Thanks, Vamsi
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