Messages in this thread | | | Date | Sun, 26 Dec 2021 20:46:50 +0300 | Subject | Re: [PATCH] clk: renesas: r8a7799[05]: Add MLP clocks | From | Sergei Shtylyov <> |
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On 25.12.2021 22:39, Nikita Yushchenko wrote:
> Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs. > > Similar to other R-Car Gen3 SoC, exact information on parent for MLP > clock on E3 and D3 is not available. However, since parent for this > clocl is not anyhow software-controllable, the only harm from this
s/clocl/clock/. :-)
> is inexact information exported via debugfs. So just keep the parent > set in the same way as with other Gen3 SoCs. > > Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> [...]
MBR, Sergey
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