Messages in this thread Patch in this message | ![/](/images/icornerl.gif) | | From | Atish Patra <> | Subject | [PATCH v1 2/2] dt-bindings: riscv: Add DT binding for RISC-V ISA extensions | Date | Fri, 24 Dec 2021 13:16:32 -0800 |
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RISC-V ISA extensions can be single letter or multi-letter names. The single letter extensions are mostly base extensions and encoded in "riscv,isa" DT property. However, parsing the multi-letter extensions via the isa string is cumbersome and is not scalable.
Add a new DT node for multi-letter extensions.
Signed-off-by: Atish Patra <atishp@rivosinc.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index aa5fb64d57eb..6c4eecf389a9 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -78,6 +78,15 @@ properties: - rv64imac - rv64imafdc + riscv,isa-ext: + description: + Identifies the specific RISC-V instruction set architecture extensions + supported by one or multiple harts. All the multi-letter extensions + should be listed here as a boolean property. This subnode can be under + /cpus or under individual cpu node. In case of former, it represent + the common ISA extensions for all harts. The name of the boolean property + must match the actual ISA extension name in all lowercase format. + $ref: "/schemas/types.yaml#/definitions/boolean" # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false -- 2.33.1
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