Messages in this thread | | | From | Greentime Hu <> | Date | Mon, 4 Oct 2021 22:13:05 +0800 | Subject | Re: [RFC PATCH v8 20/21] riscv: Optimize task switch codes of vector |
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Jisheng Zhang <jszhang3@mail.ustc.edu.cn> 於 2021年9月15日 週三 下午10:36寫道: > > On Thu, 9 Sep 2021 01:45:32 +0800 > Greentime Hu <greentime.hu@sifive.com> wrote: > > > This patch replacees 2 instructions with 1 instruction to do the same thing > > . rs1=x0 with rd != x0 is a special form of the instruction that sets vl to > > MAXVL. > > Similarly, the vector.S is newly introduced in this patch set, so could > this optimization be folded into the __vstate_save and __vstate_restore > introduction patch? Or it's better to keep this optimizaion in commit log? > Yeah, I wanted to keep the optimization commit log before, but it's ok if you think merge code is easier to read. I'll merge this patch in the next version.
> > > > Suggested-by: Andrew Waterman <andrew@sifive.com> > > Co-developed-by: Vincent Chen <vincent.chen@sifive.com> > > Signed-off-by: Vincent Chen <vincent.chen@sifive.com> > > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > > --- > > arch/riscv/kernel/vector.S | 9 +++------ > > 1 file changed, 3 insertions(+), 6 deletions(-) > > > > diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S > > index 4f0c5a166e4e..f7223c81b11a 100644 > > --- a/arch/riscv/kernel/vector.S > > +++ b/arch/riscv/kernel/vector.S > > @@ -27,8 +27,7 @@ > > #define x_vl t2 > > #define x_vcsr t3 > > #define incr t4 > > -#define m_one t5 > > -#define status t6 > > +#define status t5 > > > > ENTRY(__vstate_save) > > li status, SR_VS > > @@ -38,8 +37,7 @@ ENTRY(__vstate_save) > > csrr x_vtype, CSR_VTYPE > > csrr x_vl, CSR_VL > > csrr x_vcsr, CSR_VCSR > > - li m_one, -1 > > - vsetvli incr, m_one, e8, m8 > > + vsetvli incr, x0, e8, m8 > > vse8.v v0, (datap) > > add datap, datap, incr > > vse8.v v8, (datap) > > @@ -61,8 +59,7 @@ ENTRY(__vstate_restore) > > li status, SR_VS > > csrs CSR_STATUS, status > > > > - li m_one, -1 > > - vsetvli incr, m_one, e8, m8 > > + vsetvli incr, x0, e8, m8 > > vle8.v v0, (datap) > > add datap, datap, incr > > vle8.v v8, (datap) > >
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