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    SubjectRe: [PATCH] KVM: LAPIC: Reset timer_advance_ns if timer mode switch
    Date
    Wanpeng Li <kernellwp@gmail.com> writes:

    > From: Wanpeng Li <wanpengli@tencent.com>
    >
    > per-vCPU timer_advance_ns should be set to 0 if timer mode is not tscdeadline
    > otherwise we waste cpu cycles in the function lapic_timer_int_injected(),

    lapic_timer_int_injected is just a test, kvm_wait_lapic_expire()
    (__kvm_wait_lapic_expire()) maybe?

    > especially on AMD platform which doesn't support tscdeadline mode. We can
    > reset timer_advance_ns to the initial value if switch back to
    > tscdealine

    'tscdeadline'

    > timer mode.
    >
    > Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
    > ---
    > arch/x86/kvm/lapic.c | 6 ++++++
    > 1 file changed, 6 insertions(+)
    >
    > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
    > index 654649b..abc296d 100644
    > --- a/arch/x86/kvm/lapic.c
    > +++ b/arch/x86/kvm/lapic.c
    > @@ -1499,10 +1499,16 @@ static void apic_update_lvtt(struct kvm_lapic *apic)
    > kvm_lapic_set_reg(apic, APIC_TMICT, 0);
    > apic->lapic_timer.period = 0;
    > apic->lapic_timer.tscdeadline = 0;
    > + if (timer_mode == APIC_LVT_TIMER_TSCDEADLINE &&
    > + lapic_timer_advance_dynamic)
    > + apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
    > }
    > apic->lapic_timer.timer_mode = timer_mode;
    > limit_periodic_timer_frequency(apic);
    > }
    > + if (timer_mode != APIC_LVT_TIMER_TSCDEADLINE &&
    > + lapic_timer_advance_dynamic)
    > + apic->lapic_timer.timer_advance_ns = 0;
    > }
    >
    > /*

    --
    Vitaly

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