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    Subject[PATCH 5.8 012/232] PCI: qcom: Add support for tx term offset for rev 2.1.0
    Date
    From: Ansuel Smith <ansuelsmth@gmail.com>

    commit de3c4bf648975ea0b1d344d811e9b0748907b47c upstream.

    Add tx term offset support to pcie qcom driver need in some revision of
    the ipq806x SoC. Ipq8064 needs tx term offset set to 7.

    Link: https://lore.kernel.org/r/20200615210608.21469-9-ansuelsmth@gmail.com
    Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
    Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
    Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
    Cc: stable@vger.kernel.org # v4.5+
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/pci/controller/dwc/pcie-qcom.c | 17 ++++++++++++++++-
    1 file changed, 16 insertions(+), 1 deletion(-)

    --- a/drivers/pci/controller/dwc/pcie-qcom.c
    +++ b/drivers/pci/controller/dwc/pcie-qcom.c
    @@ -45,7 +45,13 @@
    #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10

    #define PCIE20_PARF_PHY_CTRL 0x40
    +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
    +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
    +
    #define PCIE20_PARF_PHY_REFCLK 0x4C
    +#define PHY_REFCLK_SSP_EN BIT(16)
    +#define PHY_REFCLK_USE_PAD BIT(12)
    +
    #define PCIE20_PARF_DBI_BASE_ADDR 0x168
    #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
    #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
    @@ -354,9 +360,18 @@ static int qcom_pcie_init_2_1_0(struct q
    writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
    }

    + if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
    + /* set TX termination offset */
    + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
    + val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
    + val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
    + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
    + }
    +
    /* enable external reference clock */
    val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
    - val |= BIT(16);
    + val &= ~PHY_REFCLK_USE_PAD;
    + val |= PHY_REFCLK_SSP_EN;
    writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);

    ret = reset_control_deassert(res->phy_reset);

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