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    Subject[PATCH 5.8 159/232] iommu/vt-d: Enforce PASID devTLB field mask
    Date
    From: Liu Yi L <yi.l.liu@intel.com>

    [ Upstream commit 5f77d6ca5ca74e4b4a5e2e010f7ff50c45dea326 ]

    Set proper masks to avoid invalid input spillover to reserved bits.

    Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
    Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
    Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
    Reviewed-by: Eric Auger <eric.auger@redhat.com>
    Link: https://lore.kernel.org/r/20200724014925.15523-2-baolu.lu@linux.intel.com
    Signed-off-by: Joerg Roedel <jroedel@suse.de>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    include/linux/intel-iommu.h | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
    index 04bd9279c3fb3..711bdca975be3 100644
    --- a/include/linux/intel-iommu.h
    +++ b/include/linux/intel-iommu.h
    @@ -381,8 +381,8 @@ enum {

    #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
    #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
    -#define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
    -#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
    +#define QI_DEV_EIOTLB_GLOB(g) ((u64)(g) & 0x1)
    +#define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32)
    #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
    #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
    #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
    --
    2.25.1


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