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    Subject[tip: perf/core] perf/x86/intel: Move BTS index to 47
    The following commit has been merged into the perf/core branch of tip:

    Commit-ID: d39fcc32893dac2d02900d99c38276a00cc54d60
    Gitweb: https://git.kernel.org/tip/d39fcc32893dac2d02900d99c38276a00cc54d60
    Author: Kan Liang <kan.liang@linux.intel.com>
    AuthorDate: Thu, 23 Jul 2020 10:11:07 -07:00
    Committer: Peter Zijlstra <peterz@infradead.org>
    CommitterDate: Tue, 18 Aug 2020 16:34:35 +02:00

    perf/x86/intel: Move BTS index to 47

    The bit 48 in the PERF_GLOBAL_STATUS is used to indicate the overflow
    status of the PERF_METRICS counters.

    Move the BTS index to the bit 47.

    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Link: https://lkml.kernel.org/r/20200723171117.9918-5-kan.liang@linux.intel.com
    ---
    arch/x86/include/asm/perf_event.h | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
    index fe8110a..58419e5 100644
    --- a/arch/x86/include/asm/perf_event.h
    +++ b/arch/x86/include/asm/perf_event.h
    @@ -238,11 +238,11 @@ struct x86_pmu_capability {
    /*
    * We model BTS tracing as another fixed-mode PMC.
    *
    - * We choose a value in the middle of the fixed event range, since lower
    + * We choose the value 47 for the fixed index of BTS, since lower
    * values are used by actual fixed events and higher values are used
    * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
    */
    -#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
    +#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15)

    #define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
    #define GLOBAL_STATUS_BUFFER_OVF_BIT 62
    \
     
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