Messages in this thread Patch in this message | | | From | Faiz Abbas <> | Subject | [PATCH 1/2] arm64: dts: ti: k3-am65-main: Add support for sdhci1 | Date | Sat, 11 Jul 2020 00:32:14 +0530 |
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Add support for the 2nd SDHCI controller on TI's AM654x SoCs. Although it supports upto SDR104 (100 MBps @ 200 MHz) speed mode, only enable support upto High Speed (25 MBps @ 50 MHz) for now.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 3a4effee8fba..dfb429bed56d 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -259,6 +259,30 @@ dma-coherent; }; + sdhci1: sdhci@4fa0000 { + compatible = "ti,am654-sdhci-5.1"; + reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; + clock-names = "clk_ahb", "clk_xin"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0x0>; + ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr50 = <0x8>; + ti,otap-del-sel-sdr104 = <0x7>; + ti,otap-del-sel-ddr50 = <0x4>; + ti,otap-del-sel-ddr52 = <0x4>; + ti,otap-del-sel-hs200 = <0x7>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel = <0x2>; + ti,trm-icp = <0x8>; + dma-coherent; + no-1-8-v; + }; + scm_conf: scm_conf@100000 { compatible = "syscon", "simple-mfd"; reg = <0 0x00100000 0 0x1c000>; -- 2.17.1
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